公开(公告)号：US12040293B2

公开(公告)日：2024-07-16

申请号：US18055241

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/532 ,  H01L21/02 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L24/05 ,  H01L21/02068 ,  H01L24/03 ,  H01L2224/02321 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/035 ,  H01L2224/0391 ,  H01L2224/05008 ,  H01L2224/05083 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05188 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/04953 ,  H01L2924/0535 ,  H01L2924/05994

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US10658315B2

公开(公告)日：2020-05-19

申请号：US15937339

申请日：2018-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L21/02 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20180102418A1

公开(公告)日：2018-04-12

申请号：US15420580

申请日：2017-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Han-Wen Liao ,  Xuan-You Yan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L21/32135 ,  H01L21/32137 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

公开(公告)号：US11502050B2

公开(公告)日：2022-11-15

申请号：US17170624

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L21/02 ,  H01L23/532 ,  H01L23/525 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20210071295A1

公开(公告)日：2021-03-11

申请号：US17101586

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Chih Chu ,  Chien-Hsun Pan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: C23C14/54 ,  H01L21/285 ,  C23C14/35 ,  C23C14/34 ,  H01L21/67 ,  H01J37/34

Abstract: Sputtering systems and methods are provided. In an embodiment, a sputtering system includes a chamber configured to receive a substrate, a sputtering target positioned within the chamber, and an electromagnet array over the sputtering target. The electromagnet array includes a plurality of electromagnets.

公开(公告)号：US10784114B2

公开(公告)日：2020-09-22

申请号：US16670107

申请日：2019-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Wen Liao ,  Jun-Xiu Liu ,  Chun-Chih Lin

IPC: H01L21/306 ,  H01L21/76 ,  H01L21/67 ,  H01L21/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311

Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

公开(公告)号：US10916517B2

公开(公告)日：2021-02-09

申请号：US16727628

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/532 ,  H01L23/525 ,  H01L21/02 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US10651066B2

公开(公告)日：2020-05-12

申请号：US15879651

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Powen Huang ,  Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/673 ,  H01L21/02 ,  G01D7/00 ,  G01D5/00 ,  B08B3/04

Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier using a transportation apparatus. The method further includes measuring an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool positioned on the wafer carrier during the movement of the wafer carrier. The method also includes issuing a warning when the detected environmental condition is outside a range of acceptable values.

公开(公告)号：US10354965B2

公开(公告)日：2019-07-16

申请号：US15719370

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Chun-Chih Lin ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Wen-Hao Cheng

IPC: H01L23/52 ,  H01L23/00

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

公开(公告)号：US10345716B2

公开(公告)日：2019-07-09

申请号：US15877646

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

IPC: G03F7/20

Abstract: A method for fault detection in a fabrication system is provided. The method includes transferring a reticle carrier containing a reticle from an original position to a destination position. The method further includes detecting environmental condition in the reticle carrier during the transfer of the reticle carrier using a metrology tool that is positioned at the reticle carrier. The method also includes issuing a warning when the detected environmental condition is outside a range of acceptable values.