公开(公告)号：US20080144407A1

公开(公告)日：2008-06-19

申请号：US12037884

申请日：2008-02-26

申请人： Robert P. Masleid ,  James B. Burr

发明人： Robert P. Masleid ,  James B. Burr

IPC分类号： G11C7/00 ,  G06F17/50

CPC分类号： H03K5/1252 ,  H03K5/133 ,  H03K17/6872 ,  H03K19/00361

摘要： Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

摘要翻译： 堆叠式逆变器延时链。 根据本发明的第一实施例，两个p型器件的串联堆叠耦合到三个n型器件的串联堆叠，形成堆叠的反相器，其包括期望的延迟，管芯面积和功率特性。 两个堆叠的反相器耦合在一起以形成堆叠的反相器延迟链，其在与常规逆变器的常规延迟链相比在管芯面积，主动和无源功耗方面更有效。

公开(公告)号：US07323367B1

公开(公告)日：2008-01-29

申请号：US11799496

申请日：2007-05-01

申请人： Mike Pelham ,  James B. Burr

发明人： Mike Pelham ,  James B. Burr

IPC分类号： H01L21/82 ,  H01L21/335 ,  H01L21/8238

CPC分类号： H01L21/823892 ,  H01L23/535 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0928 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

摘要翻译： 提供和描述了用于在表面阱区域中为MOSFETs布置体偏置的对角深阱区域。

公开(公告)号：US07205758B1

公开(公告)日：2007-04-17

申请号：US10771015

申请日：2004-02-02

申请人： Robert Paul Masleid ,  James B. Burr

发明人： Robert Paul Masleid ,  James B. Burr

IPC分类号： G01R31/26

CPC分类号： H03K19/0027 ,  G01R31/2621 ,  H03K2217/0018

摘要： Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias, voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

摘要翻译： 用于调整阈值电压的系统和方法。 测量集成电路的晶体管的阈值电压。 当施加到晶体管的体阱时，偏置电压校正阈值电压和晶体管的期望阈值电压之间的差异。 偏置电压被编码到集成电路的非易失性存储器中。 非易失性存储器可以是数字和/或模拟的。

公开(公告)号：US06624687B1

公开(公告)日：2003-09-23

申请号：US09872828

申请日：2001-05-31

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： G05F302

CPC分类号： G05F3/24

摘要： A method and structure for supply gating low power electronic components uses low threshold gating transistors. The low power components operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be minimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

公开(公告)号：US06605971B1

公开(公告)日：2003-08-12

申请号：US09873154

申请日：2001-06-01

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H03K3356

CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/356165

摘要： Low voltage latches are designed such that the latch components are comprised of low threshold transistors. To overcome the effects of leakage current and ensure proper latch operation, according to the invention, the channel widths of the low threshold transistors making up the feedback components of the latch are larger than the channel widths of the low threshold transistors making up the storage components of the latch. Using the method and structure of the invention, the voltage scalability of the latch is significantly increased. One embodiment of the invention allows for minimum supply voltages of around 120 millivolts, an improvement of over six hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

摘要翻译： 低压锁存器被设计成使得锁存器组件由低阈值晶体管组成。 为了克服泄漏电流的影响并确保适当的锁存操作，根据本发明，构成锁存器的反馈分量的低阈值晶体管的沟道宽度大于组成存储组件的低阈值晶体管的沟道宽度 的闩锁。 使用本发明的方法和结构，锁存器的电压可伸缩性显着增加。 本发明的一个实施例允许约120毫伏的最小电源电压，与典型的现有技术的800毫伏的最小电压要求相比，改善了超过百分之六百。

公开(公告)号：US06552601B1

公开(公告)日：2003-04-22

申请号：US09872822

申请日：2001-05-31

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： G05F110

CPC分类号： G05F3/242

摘要： A method for supply gating low power electronic devices uses low threshold gating transistors. The low power devices operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be optimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

摘要翻译： 用于供电选通低功率电子器件的方法使用低阈值门控晶体管。 低功率器件的工作电压低于1伏特，通常在150至400毫伏的范围内。 使用低门限门控晶体管，可以通过使用以下四种方法中的任何一种或其组合来优化器件的漏电流以及因此的待机功率耗散，包括：过载驱动低阈值门控晶体管; 过驱动低门限门控晶体管关闭; 将极低阈值器件晶体管与低阈值门控晶体管相结合; 以及提供具有反偏压的低阈值选通晶体管。

公开(公告)号：US06501295B1

公开(公告)日：2002-12-31

申请号：US09872840

申请日：2001-06-01

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L2500

CPC分类号： H03K19/17784 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/17792 ,  H01L2924/00

摘要： Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

摘要翻译： 可编程逻辑结构包括在非常低的电源电压下工作的逻辑块。 根据本发明，传输晶体管位于逻辑块之间。 由于本发明的逻辑块在非常低的电源电压下工作，所以传输晶体管可能被过载驱动，从而降低了增加的电阻。 在本发明的一个实施例中，传输晶体管是低阈值晶体管。 在该实施例中，传输晶体管也被过驱动以减少泄漏电流并进一步隔离逻辑块。

公开(公告)号：US06303444B1

公开(公告)日：2001-10-16

申请号：US09693715

申请日：2000-10-19

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L21336

CPC分类号： H01L21/823892 ,  H01L27/0738 ,  H01L27/0921 ,  H01L29/1083 ,  H01L29/78 ,  H01L29/783

摘要： A method for providing low power MOS devices that include buried wells specifically designed to provide a resistive path between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between clock cycles.

摘要翻译： 一种用于提供低功率MOS器件的方法，其包括专门设计用于在器件的散装材料和阱接触之间提供电阻路径的掩埋阱。 通过提供电阻路径，将等效的RC电路引入器件，其允许体材料电势跟踪栅极电位，从而有利地降低器件导通时的阈值电压，并在器件关断时提高阈值电压。 此外，引入电阻路径还允许大量材料电位被控制并且稳定在时钟周期之间的平衡电位。

公开(公告)号：US06218708B1

公开(公告)日：2001-04-17

申请号：US09030030

申请日：1998-02-25

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L2976

CPC分类号： H01L27/092 ,  H01L29/1087

摘要： An MOS device has source and drain regions of a first conductivity formed in a well of a second conductivity, the well of the second conductivity being formed in an upper surface of a bulk material of the first conductivity. Source and drain potentials are applied to the source and drain regions, respectively, while a separate bias potential is routed to the well through a conductive sub-surface layer of the second conductivity which is located spaced from and beneath an upper surface of the bulk material and which is shorted to the well.

摘要翻译： MOS器件具有在第二导电性阱中形成的具有第一导电性的源区和漏区，第二导电的阱形成在第一导电性的散装材料的上表面中。 源极和漏极电位分别施加到源极和漏极区域，而单独的偏置电势通过第二导电性的导电子表面层被引导到阱，该导电子表面层与散装材料的上表面间隔开并在其下面 并且与井短路。

公开(公告)号：US6121666A

公开(公告)日：2000-09-19

申请号：US884152

申请日：1997-06-27

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/7835 ,  H01L29/1045 ,  H01L29/1083

摘要： A method for making an asymmetric MOS device having a notched gate oxide is disclosed herein. Such MOS devices have a region of a gate oxide adjacent to either the source or drain that is thinner than the remainder of the gate oxide. The thin "notched" region of gate oxide lies over a region of the device's channel region that has been engineered to have a relatively "high" threshold voltage (near 0 volts) in comparison to the remainder of the channel region. This region of higher threshold voltage may be created by a pocket region of increased dopant concentration abutting the source or the drain (but not both) and proximate the channel region. The pocket region has the opposite conductivity type as the source and drain. A device so structured behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket region is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET. If the pocket region is located under the drain, the reverse arrangement will be true. The region of thin gate oxide (the notched region) provides a higher gate capacitance than the remaining regions of thicker gate oxide. Thus, the channel region under the notched region of gate oxide has a relatively high concentration of mobile charge carriers in the channel region.

摘要翻译： 本文公开了制造具有缺口栅极氧化物的非对称MOS器件的方法。 这种MOS器件具有与源极或漏极相邻的栅极氧化物的区域，其比栅极氧化物的其余部分更薄。 栅极氧化物的薄的“缺口”区域位于器件沟道区域的一个区域上，与沟道区域的其余部分相比，其设计为具有相对“高”阈值电压（接近0伏）。 可以通过邻近源极或漏极（但不是两者）并且靠近沟道区的增加的掺杂剂浓度的袋区域来产生较高阈值电压的该区域。 口袋区域具有与源极和漏极相反的导电类型。 如此结构的器件类似于串联的两个伪MOS器件：“源FET”和“漏极FET”。 如果口袋区域位于源极下方，则源FET将具有比漏极FET更高的阈值电压和更短的有效沟道长度。 如果口袋区域位于排水口下方，则相反的布置将成立。 薄栅极氧化物（缺口区域）的区域提供比栅极氧化物较厚的剩余区域更高的栅极电容。 因此，栅极氧化物的缺口区域下方的沟道区域在沟道区域中具有较高浓度的移动电荷载流子。