公开(公告)号：US20240170446A1

公开(公告)日：2024-05-23

申请号：US18508071

申请日：2023-11-13

Applicant: STMicroelectronics International N.V.

Inventor： Sandrine LHOSTIS ,  Bassel AYOUB ,  Laurent FREY

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present description concerns a method of assembly of a first assembly layer comprising a first copper region at a first surface and of a second assembly layer comprising a second region made of oxide or of an oxidized metal at a second surface, wherein the first and second surfaces are assembled by means of a hybrid bonding such that the entire first copper region is placed into contact with the oxide or the oxidized metal of the second region.

公开(公告)号：US11991028B1

公开(公告)日：2024-05-21

申请号：US18059103

申请日：2022-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Iztok Bratuz ,  Vinko Kunc ,  Maksimiljan Stiglic

IPC: H04L25/49

CPC classification number: H04L25/4904

Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.

公开(公告)号：US20240146092A1

公开(公告)日：2024-05-02

申请号：US18491322

申请日：2023-10-20

Applicant: STMicroelectronics International N.V.

Inventor： Simone BIANCHI ,  Vanni POLETTO

IPC: H02J7/34 ,  H02M3/158

CPC classification number: H02J7/342 ,  H02M3/158 ,  H02J2207/20

Abstract: A circuit for use, e.g., as current sense amplifier in a DC-DC converter in a hybrid vehicle includes a first input node and a second input node, configured to have an input voltage signal applied therebetween, a floating-ground input stage configured to operate between a first supply voltage and a second non-zero supply voltage and to convert into a current signal the input voltage signal applied between the first input node and the second input node. The circuit includes an output stage configured to receive the current signal from the floating-ground input stage and to convert the current signal back to an output voltage signal referred to ground. The output voltage referred to ground is a replica of the input voltage signal applied between the first input node and the second input node.

公开(公告)号：US20240112748A1

公开(公告)日：2024-04-04

申请号：US18228118

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Tanuj KUMAR ,  Hitesh CHAWLA ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G11C29/12015 ,  G11C29/32 ,  G11C2029/1204

Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.

公开(公告)号：US20240088711A1

公开(公告)日：2024-03-14

申请号：US17941199

申请日：2022-09-09

Applicant: STMicroelectronics Asia Pacific Pte Ltd. ,  STMicroelectronics International N.V.

Inventor： Baranidharan Karuppusamy ,  Abhay Jaisen Bhanushali

IPC: H02J50/10 ,  H02J7/00 ,  H02J50/80

CPC classification number: H02J50/10 ,  H02J7/00711 ,  H02J7/00712 ,  H02J50/80 ,  H02J2207/20

Abstract: A method for operating a wireless power transmitter includes: receiving a power control command from a wireless power receiver; computing a potential voltage change for a transmitter voltage of the wireless power transmitter in accordance with a target transmitter power and a present value of a transmitter current of the wireless power transmitter; comparing the potential voltage change with a discrete step size of a supply voltage; and in response to determining that the magnitude of the potential voltage change is equal to or larger than the discrete step size of the supply voltage, adjusting the transmitter power by: adjusting the supply voltage by one or more discrete steps; and controlling a power conversion circuit of the wireless power transmitter using a target current value computed in accordance with the target transmitter power and the adjusted supply voltage.

公开(公告)号：US20240071546A1

公开(公告)日：2024-02-29

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

CPC classification number: G11C29/1201 ,  G11C29/36 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/3602

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20240071429A1

公开(公告)日：2024-02-29

申请号：US18233562

申请日：2023-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Nitin CHAWLA ,  Promod KUMAR ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1009 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/12

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

公开(公告)号：US20240069096A1

公开(公告)日：2024-02-29

申请号：US18228048

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G01R31/317 ,  G11C11/418 ,  G11C11/419

CPC classification number: G01R31/31724 ,  G11C11/418 ,  G11C11/419

Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.

公开(公告)号：US11901865B2

公开(公告)日：2024-02-13

申请号：US17931863

申请日：2022-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Nitin Jain

IPC: H03B5/06 ,  H03B5/36

CPC classification number: H03B5/364 ,  H03B5/06 ,  H03B5/366 ,  H03B2200/0082 ,  H03B2200/0094

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

公开(公告)号：US11900240B2

公开(公告)日：2024-02-13

申请号：US17023144

申请日：2020-09-16

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Manuj Ayodhyawasi ,  Thomas Boesch ,  Surinder Pal Singh

IPC: G06N3/06 ,  G06F1/32 ,  G06F9/50 ,  G06F1/08 ,  G06N3/063 ,  G06N3/082 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06N3/063 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/5027 ,  G06N3/082

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.