公开(公告)号：US10199239B2

公开(公告)日：2019-02-05

申请号：US14823341

申请日：2015-08-11

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC分类号： H01L21/52 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

摘要： A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

公开(公告)号：US20190027380A1

公开(公告)日：2019-01-24

申请号：US16070893

申请日：2017-02-07

申请人： MITSUBISHI MATERIALS CORPORATION

发明人： Shuji Nishimoto ,  Yoshiyuki Nagatomo

IPC分类号： H01L21/52 ,  H01L23/00

摘要： A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.

公开(公告)号：US10186496B2

公开(公告)日：2019-01-22

申请号：US15474727

申请日：2017-03-30

申请人： ROHM CO., LTD.

发明人： Akihiro Kimura ,  Takeshi Sunaga

IPC分类号： H01L21/00 ,  H01L23/52 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L21/52

摘要： A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

公开(公告)号：US10186466B2

公开(公告)日：2019-01-22

申请号：US15728969

申请日：2017-10-10

申请人： STMicroelectronics (Grenoble 2) SAS

发明人： Benoit Besancon ,  Luc Petit

IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L21/58 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

摘要： An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.

公开(公告)号：US10181447B2

公开(公告)日：2019-01-15

申请号：US15493917

申请日：2017-04-21

申请人： Invensas Corporation

发明人： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/52 ,  H01L25/065 ,  H01L23/538

摘要： A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package. The conductive structure may be patterned to form external contacts. At least some of the external contacts may overlie the microelectronic element.

公开(公告)号：US10173890B2

公开(公告)日：2019-01-08

申请号：US15628978

申请日：2017-06-21

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Jean-Charles Souriau

IPC分类号： B81B7/00 ,  H01L23/057 ,  H01L23/18 ,  H01L23/498 ,  H01L23/10 ,  H01L21/52

摘要： A box for a microelectronic device includes a first portion and a second portion able to be assembled in order to define, in an assembled position, a housing space for the microelectronic device. A face of the first portion is facing a face of the second portion in the assembled position. The first zones facing the faces form an interface for attaching the first portion and second portion. The second zones face faces forming a cavity for receiving the microelectronic device. At least one among the first portion and the second portion includes at least one element for electrical connection. The first portion and the second portion can apply at least one connection pad of the microelectronic device on the element for connection in the assembled position.

公开(公告)号：US10170347B2

公开(公告)日：2019-01-01

申请号：US15128804

申请日：2015-02-27

申请人： TOKYO ELECTRON LIMITED

发明人： Yutaka Fujino

IPC分类号： H01L21/67 ,  C23C16/44 ,  C23C16/455 ,  C23C16/54 ,  H01L21/52 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687

摘要： A substrate processing system for performing a process with respect to a plurality of substrates includes an annular process chamber configured to accommodate the plurality of substrates and to perform a predetermined process on the plurality of substrates, a cassette mounting part configured to mount a cassette which accommodates the plurality of substrates, and a substrate transfer mechanism configured to transfer the plurality of substrates between the annular process chamber and the cassette mounting part. The plurality of substrates is concentrically disposed within the annular process chamber in a plane view.

公开(公告)号：US10163762B2

公开(公告)日：2018-12-25

申请号：US14735229

申请日：2015-06-10

申请人： Vishay General Semiconductor LLC

发明人： Hui-Ying Ding ,  Pengnian Wang ,  Tao Yu ,  Jun-Feng Liu ,  Jun-Kai Bai ,  Chih-Ping Peng

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L21/52 ,  H01L21/56 ,  H01L23/31 ,  H01L21/60

摘要： A semiconductor assembly includes a semiconductor die comprising lower and upper electrical contacts. A lead frame having a lower die pad is electrically and mechanically connected to the lower electrical contact of the die. An upper conductive member has a first portion electrically and mechanically connected to the upper electrical contact of the die. A lead terminal has a surface portion electrically and mechanically connected to a second portion of the conductive member. The surface portion of the lead terminal and/or the second portion of the conductive member has a series of grooves disposed therein. Packaging material encapsulates the semiconductor die, at least a portion of the lead frame, at least a portion of the upper conducive member and at least a portion of the lead terminal.

公开(公告)号：US10163755B2

公开(公告)日：2018-12-25

申请号：US15498321

申请日：2017-04-26

申请人： Micron Technology, Inc.

发明人： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC分类号： H01L21/52 ,  H01L21/54 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/44 ,  H01L25/00 ,  H01L25/18 ,  H01L23/053 ,  H01L23/367 ,  H01L23/373

摘要： Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US10115605B2

公开(公告)日：2018-10-30

申请号：US15203732

申请日：2016-07-06

申请人： RJR Technologies, Inc.

发明人： Richard J. Ross ,  John Ni ,  Raymond J. Bregante ,  Biao Fu ,  Michael Bregante ,  Cresencio Amparo

IPC分类号： H01L21/52 ,  H01L21/50

摘要： The present disclosure describes a sealing processes and structure for sealing air cavity electronic packages using a thermosetting, thermal plastic, other known or as yet unknown adhesives, or hybrid combinations of such adhesive(s). Processes disclosed comprise steps of providing a base and a lid, with at least one of the base and the lid having a mating surface coated with the adhesive. Initially, an air gap is maintained between the base, the lid, and the adhesive and a vacuum is generated around the base, the lid, and the adhesive. Once the vacuum has been generated, the base and the lid are mated to create a mated package assembly with a vacuum therein. After the mating, the mated package assembly is heated to a curing temperature to cure the adhesive, and pressure may be applied as well. Because the air within the mated package assembly has been evacuated prior to heating, there is no air pressure build-up therein, reducing or eliminating the presence of blowouts and pin holes.