公开(公告)号：US20080251826A1

公开(公告)日：2008-10-16

申请号：US11747527

申请日：2007-05-11

Applicant: Jack Lee ,  Herbert Lu ,  Marvin Liu ,  Peter Pong

Inventor： Jack Lee ,  Herbert Lu ,  Marvin Liu ,  Peter Pong

IPC: H01L27/108 ,  H01L21/46

CPC classification number: H01L27/10894 ,  H01L21/187 ,  H01L27/105 ,  H01L27/10844 ,  H01L27/11517

Abstract: A method for manufacturing a multi-layer semiconductor structure is disclosed. First, a first wafer comprising a first semiconductor device structure and a second wafer comprising a substrate and a single crystal silicon layer are provided, and the first and second wafers are combined in which a surface of the first wafer having the first semiconductor device structure is in contact with a surface of the second wafer having the single crystal silicon layer. A glue layer and a dielectric layer can be employed to combine the first and second wafers. Afterwards, a process for manufacturing a second semiconductor device structure is performed on the single crystal silicon layer.

Abstract translation: 公开了一种制造多层半导体结构的方法。 首先，提供包括第一半导体器件结构的第一晶片和包括衬底和单晶硅层的第二晶片，并且组合第一和第二晶片，其中具有第一半导体器件结构的第一晶片的表面是 与具有单晶硅层的第二晶片的表面接触。 可以使用胶层和电介质层来组合第一和第二晶片。 之后，在单晶硅层上进行第二半导体器件结构的制造工序。

公开(公告)号：US07427569B2

公开(公告)日：2008-09-23

申请号：US11307801

申请日：2006-02-23

Applicant: Tza-Hao Wang ,  Jin-Yang Huang ,  Hung-Kwei Liao ,  Ming-Sheng Tung

Inventor： Tza-Hao Wang ,  Jin-Yang Huang ,  Hung-Kwei Liao ,  Ming-Sheng Tung

IPC: H01L21/00 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/32139 ,  H01L21/321 ,  H01L21/32135

Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.

Abstract translation: 描述金属蚀刻工艺。 提供其上具有介电层的基板。 在电介质层上形成铝 - 铜合金层。 在铝 - 铜合金层上形成硬掩模层。 在硬掩模层上形成图案化的光致抗蚀剂层，然后对硬掩模层进行图案化。 进行热处理工艺。 热处理过程在大于300℃的温度下进行至少3分钟的时间。 此后，使用图案化的硬掩模层作为蚀刻掩模蚀刻铝 - 铜合金层。 由于热处理，铝 - 铜合金层内的金属沉淀物（CuAl 2 N 2）被消除，因此改善了金属蚀刻工艺。

公开(公告)号：US20080219046A1

公开(公告)日：2008-09-11

申请号：US12000407

申请日：2007-12-12

Applicant: Ming-Jung Chen ,  Te-Sheng Chao ,  Philip H. Yeh

Inventor： Ming-Jung Chen ,  Te-Sheng Chao ,  Philip H. Yeh

IPC: G11C11/00 ,  G11C7/04

CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078

Abstract: A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature.

Abstract translation: 公开了一种用于相变存储器的写入方法。 写入方法将第一写入脉冲信号输入到相变存储器，以将相变存储器加热到高于第一温度，并将第二写入脉冲信号输入到相变存储器，以将相变存储器保持在第二温度。

公开(公告)号：US20080166866A1

公开(公告)日：2008-07-10

申请号：US11763753

申请日：2007-06-15

Applicant: CHIANG YUH REN

Inventor： CHIANG YUH REN

IPC: H01L21/02

CPC classification number: H01L21/28247 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/76897

Abstract: A method for forming a gate structure with a pulled-back conductive layer and the use of the method are provided. The method conducts a local, not global, pull-back process on the conductive layer of the gate structure at the position intended for contact window formation, wherein the pull-back process is conducted after rapid thermal oxidation to prevent CBCB short, CB open and/or CBGC short.

Abstract translation: 提供一种用于形成具有拉回导电层的栅极结构的方法和该方法的使用。 该方法在用于接触窗口形成的位置处在栅极结构的导电层上进行局部的，而不是全局的拉回过程，其中拉伸过程在快速热氧化之后进行以防止CBCB短，CB开放和 /或CBGC短。

公开(公告)号：US07383095B2

公开(公告)日：2008-06-03

申请号：US11123974

申请日：2005-05-06

Applicant: Yungyao Lee ,  Ben Liou

Inventor： Yungyao Lee ,  Ben Liou

IPC: G06F19/00

CPC classification number: G03F9/7046 ,  G03F7/70508 ,  G03F7/70633 ,  G03F9/7003 ,  G03F9/7011 ,  G03F9/7019 ,  H01L22/20

Abstract: An integration system for obtaining a set of overlay offset parameters of a first process layer which is going to be formed in an assigned photolithography tool with an assigned mask and an assigned pre-tool. By using the integration system, the set of overlay offset parameters of the first process layer can be precisely predicted based on summing the historic-recorded set of overlay offset parameters and the bias values including a mask bias value, a photolithography tool bias value and a pit-tool bias value. Therefore, the overlay offset parameters corresponding to the same process layer can be well integrated and managed. Hence, the cost and time due to performing the test run can be saved and the throughput can be increased as well.

Abstract translation: 一种用于获得第一处理层的叠加偏移参数集合的集成系统，该第一处理层将在具有分配的掩模和分配的预工具的分配的光刻工具中形成。 通过使用积分系统，可以基于对历史记录的叠加偏移参数集合和包括掩模偏置值，光刻工具偏置值和偏移值的偏置值相加来精确地预测第一处理层的叠加偏移参数集合 坑工具偏差值。 因此，对应于相同处理层的覆盖偏移参数可以很好的集成和管理。 因此，可以节省由于执行测试运行而导致的成本和时间，并且也可以提高吞吐量。

公开(公告)号：US20080105934A1

公开(公告)日：2008-05-08

申请号：US12003346

申请日：2007-12-21

Applicant: Heng Kai Hsu

Inventor： Heng Kai Hsu

IPC: H01L29/78

CPC classification number: H01L21/26586 ,  H01L21/28061 ,  H01L29/78

Abstract: The present gate structure comprises a gate oxide layer positioned on a substrate, a conductive stack positioned on the gate oxide layer, a passivation layer positioned on the sidewall of the conductive stack, and a cap layer positioned on the conductive stack. The conductive stack includes a polysilicon layer, a tungsten nitride layer, and a tungsten layer. The passivation layer can be made of silicon oxide, silicon nitride, or silicon oxynitride. The present method for preparing the gate structure comprises steps of forming a gate oxide layer, a conductive stack, and a cap layer on a semiconductor substrate in sequence, removing a portion of the gate oxide layer, the conductive stack, and the cap layer to form at least one opening, implanting silicon ions into the sidewall of the conductive stack, and performing a thermal treating process to transform the sidewall with silicon ions into a passivation layer.

Abstract translation: 本栅极结构包括位于衬底上的栅极氧化物层，位于栅极氧化物层上的导电叠层，位于导电叠层的侧壁上的钝化层以及位于导电叠层上的盖层。 导电叠层包括多晶硅层，氮化钨层和钨层。 钝化层可以由氧化硅，氮化硅或氮氧化硅制成。 制备栅极结构的本方法包括以下步骤：依次在半导体衬底上形成栅极氧化层，导电叠层和覆盖层，去除栅极氧化物层，导电叠层和盖层的一部分，以 形成至少一个开口，将硅离子注入到导电叠层的侧壁中，以及执行热处理工艺以将侧壁与硅离子转变成钝化层。

公开(公告)号：US20080102597A1

公开(公告)日：2008-05-01

申请号：US11615847

申请日：2006-12-22

Applicant: Su Chen Lai ,  Andy Wu

Inventor： Su Chen Lai ,  Andy Wu

IPC: H01L21/76

CPC classification number: H01L21/76237 ,  H01L21/823462 ,  H01L21/823481

Abstract: A method for preparing a gate oxide layer first forms a mask layer including at least one opening on a semiconductor substrate, and forms a trench in the semiconductor substrate below the opening, wherein the trench surrounds an active area. The opening is enlarged to expose a portion of the semiconductor substrate at the sides of the trench, i.e., to expose the edge of the active area, and an implanting process is then performed to implant nitrogen-containing dopants into the exposed semiconductor substrate below the enlarged opening. Subsequently, the mask layer is removed to expose the semiconductor substrate in the active area, and a thermal treating process is performed to form a gate oxide layer on the upper surface of the semiconductor substrate in the active area. The nitrogen-containing dopants can inhibit the reaction rate of the thermal oxidation of the semiconductor substrate during the thermal treating process.

Abstract translation: 首先制备栅极氧化层的方法形成掩模层，该掩模层包括在半导体衬底上的至少一个开口，并且在半导体衬底的沟槽下面形成沟槽，其中沟槽围绕有源区。 开口被放大以暴露沟槽侧面的半导体衬底的一部分，即暴露有源区的边缘，然后进行注入工艺以将含氮掺杂剂注入暴露的半导体衬底的下方 扩大开放 随后，去除掩模层以在有源区域中露出半导体衬底，并且进行热处理工艺以在有源区域中的半导体衬底的上表面上形成栅氧化层。 含氮掺杂剂可以抑制热处理过程中半导体衬底的热氧化反应速率。

公开(公告)号：US20080096346A1

公开(公告)日：2008-04-24

申请号：US11561957

申请日：2006-11-21

Applicant: Ching Lee ,  Chin Wen Lee ,  Chin Long Hung ,  Zheng Cheng Chen

Inventor： Ching Lee ,  Chin Wen Lee ,  Chin Long Hung ,  Zheng Cheng Chen

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L29/66181

Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.

Abstract translation: 制备沟槽电容器结构的方法首先在衬底中形成至少一个沟槽，并且在沟槽的底部形成电容器结构，其中电容器结构包括位于沟槽的下外表面上的掩埋底电极， 覆盖所述底部电极的内表面的第一电介质层和位于所述电介质层的表面上的顶部电极。 随后，在顶部电极上方的第一介电层的表面上形成轴环绝缘层，然后在轴环绝缘层中形成第一导电块。 具有掺杂剂的第二导电块形成在第一导电块上，并且执行热处理工艺以将掺杂剂从第二导电块扩散到半导体衬底的上部以形成掩埋导电区域。

公开(公告)号：US07344995B2

公开(公告)日：2008-03-18

申请号：US11078435

申请日：2005-03-14

Applicant: Hung Yueh Lu ,  Hong Long Chang ,  Yung Kai Lee ,  Chih Hao Chang

Inventor： Hung Yueh Lu ,  Hong Long Chang ,  Yung Kai Lee ,  Chih Hao Chang

IPC: H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/3086

Abstract: The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to form at least one concavity. A second mask is formed on the surface of the prepared structure, a second etching process is then performed to remove the second mask on the concavity, and a third etching process is performed subsequently to extend the depth of the concavity into the substrate. To prepare a conductor with high aspect ratio in the substrate, the first mask and the second mask are preferably made of dielectric material or metal. In addition, to prepare a trench with high aspect ratio in a silicon substrate, the first mask and the second mask are preferably made of dielectric material.

Abstract translation: 本发明公开了一种制备具有高纵横比的结构的方法，其可以是沟槽或导体。 在衬底上形成第一掩模，并且执行第一蚀刻工艺以移除由第一掩模未覆盖的衬底以形成至少一个凹部。 在制备的结构的表面上形成第二掩模，然后执行第二蚀刻工艺以去除凹部上的第二掩模，并且随后执行第三蚀刻工艺以将凹部的深度延伸到衬底中。 为了在衬底中制备具有高纵横比的导体，第一掩模和第二掩模优选由介电材料或金属制成。 此外，为了在硅衬底中制备具有高纵横比的沟槽，第一掩模和第二掩模优选由电介质材料制成。

公开(公告)号：US20080057640A1

公开(公告)日：2008-03-06

申请号：US11559062

申请日：2006-11-13

Applicant: LI-CHENG TENG ,  CHUN-WEI YU ,  CHUN-CHONG FU ,  YUAN-MING CHANG

Inventor： LI-CHENG TENG ,  CHUN-WEI YU ,  CHUN-CHONG FU ,  YUAN-MING CHANG

IPC: H01L21/8244

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10852

Abstract: A method for fabricating a first electrode of a capacitor is described. A substrate comprising an insulating layer formed thereon is provided. The insulating layer has an opening. A silicon layer is formed on the insulating layer. The silicon layer is transformed to a hemispherical grain layer. An etching process is performed to remove a portion of the hemispherical grain layer outside the opening.

Abstract translation: 描述制造电容器的第一电极的方法。 提供了包括其上形成的绝缘层的基板。 绝缘层具有开口。 在绝缘层上形成硅层。 将硅层转变为半球形晶粒层。 进行蚀刻处理以去除开口外部的半球形晶粒层的一部分。