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公开(公告)号：US07342845B2
公开(公告)日：2008-03-11
申请号：US11320789
申请日：2005-12-30
Applicant: Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
Inventor： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
IPC: G11C7/00
CPC classification number: G11C5/143 , G11C5/147 , G11C11/413
Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
Abstract translation: 提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。 该装置可以包括存储器阵列，睡眠装置和钳位电路。 钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。
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公开(公告)号：US07326972B2
公开(公告)日：2008-02-05
申请号：US10880988
申请日：2004-06-30
Applicant: Maged M. Ghoneima , Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
Inventor： Maged M. Ghoneima , Muhammad M. Khellah , James W. Tschanz , Yibin Ye , Vivek K. De
IPC: H01L27/10
CPC classification number: G06F13/4217 , G11C7/1048 , H01L23/5222 , H01L2924/0002 , H01L2924/00
Abstract: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.
Abstract translation: 一种器件包括具有多个用于传输信号的电路路径的互连结构。 电路路径以不同的速度传送信号，以减少相邻电路路径之间的耦合电容效应。
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公开(公告)号：US07268569B2
公开(公告)日：2007-09-11
申请号：US11027696
申请日：2004-12-28
Applicant: Arman Vassighi , Ali Keshavarzi , Vivek K De
Inventor： Arman Vassighi , Ali Keshavarzi , Vivek K De
IPC: G01R31/02
CPC classification number: G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5006
Abstract: A thermal feedback loop controls leakage current during burn-in of a circuit.
Abstract translation: 热反馈回路控制电路老化期间的漏电流。
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公开(公告)号：US07247930B2
公开(公告)日：2007-07-24
申请号：US10955383
申请日：2004-09-30
Applicant: Siva G. Narendra , James W. Tschantz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
Inventor： Siva G. Narendra , James W. Tschantz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC: H01L23/495
CPC classification number: H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.
Abstract translation: 公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电源管理裸片。
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公开(公告)号：US07230842B2
公开(公告)日：2007-06-12
申请号：US11225912
申请日：2005-09-13
Applicant: Muhammad M. Khellah , Dinesh Somasekhar , Nam Sung Kim , Yibin Ye , Vivek K. De , Kevin Zhang , Bo Zheng
Inventor： Muhammad M. Khellah , Dinesh Somasekhar , Nam Sung Kim , Yibin Ye , Vivek K. De , Kevin Zhang , Bo Zheng
IPC: G11C11/00
CPC classification number: G11C11/412 , Y10S257/903
Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.
Abstract translation: 对于一个公开的实施例，一种装置包括耦合在单元电压节点和存储节点之间的第一p型装置，耦合在存储节点和参考电压节点之间的n型装置和耦合在第二p型装置之间 存储节点响应于选择线上的信号到位线。 衬底中的形成第一p型器件和第二p型器件的扩散区域的至少一侧基本对齐。 还公开了其他实施例。
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Patent Agency Ranking
公开(公告)号：US07208963B2
公开(公告)日：2007-04-24
申请号：US10977145
申请日：2004-10-29
Applicant: Gerhard Schrom , Peter Hazucha , Donald S. Gardner , Vivek K. De , Tanay Karnik
Inventor： Gerhard Schrom , Peter Hazucha , Donald S. Gardner , Vivek K. De , Tanay Karnik
CPC classification number: G01R15/18
Abstract: A method and apparatus is described according to various embodiments, for flowing current from one region of a coil to another region of the coil. The flowing induces—through flux linkage —a voltage across a second coil. A second current substantially does not flow though the second coil. The method and apparatus also includes measuring the current with the voltage between the two coils.
Abstract translation: 根据各种实施例描述了用于将电流从线圈的一个区域流动到线圈的另一个区域的方法和装置。 流过的感应通量 - 跨越第二个线圈的电压。 第二电流基本上不会流经第二线圈。 该方法和装置还包括用两个线圈之间的电压测量电流。
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公开(公告)号：US07206249B2
公开(公告)日：2007-04-17
申请号：US10956195
申请日：2004-09-30
Applicant: Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen H. Tang , Vivek K. De
Inventor： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen H. Tang , Vivek K. De
IPC: G11C5/14
CPC classification number: G11C11/413
Abstract: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
Abstract translation: 描述了一种方法，其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。 电压超过另一个电压，运算放大器将驱动节点没有晶体管的帮助。 电压有助于反馈回路在SRAM内的单元上建立一个压降。
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公开(公告)号：US07190286B2
公开(公告)日：2007-03-13
申请号：US11314236
申请日：2005-12-22
Applicant: Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I. Ismail
Inventor： Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I. Ismail
CPC classification number: G06F13/4072 , Y02D10/14 , Y02D10/151
Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。
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公开(公告)号：US07102358B2
公开(公告)日：2006-09-05
申请号：US10880337
申请日：2004-06-29
Applicant: Ali Keshavarzi , Fabrice Paillet , Muhammad M Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H Tang , Mohsen Alavi , Vivek K De
Inventor： Ali Keshavarzi , Fabrice Paillet , Muhammad M Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H Tang , Mohsen Alavi , Vivek K De
IPC: G01R31/26
CPC classification number: G01R31/2621 , G01R19/16571
Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
Abstract translation: 由于过电压状态，晶体管可能具有劣化特性。 可以感测劣化特性以确定晶体管先前已经经受过压状态。
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公开(公告)号：US07072205B2
公开(公告)日：2006-07-04
申请号：US10716755
申请日：2003-11-19
Applicant: Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
Inventor： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
CPC classification number: G11C11/4094 , G11C11/404 , G11C11/4076 , G11C11/4085
Abstract: A row of floating-body single transistor memory cells is written to in two phases.
Abstract translation: 一行浮体单晶体管存储单元分两个阶段写入。
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