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    DRAM Row Management for Processing in Memory
    121.
    发明公开
    DRAM Row Management for Processing in Memory 审中-公开

    公开(公告)号：US20240004584A1

    公开(公告)日：2024-01-04

    申请号：US17855109

    申请日：2022-06-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Niti Madan ,  Yasuko Eckert ,  Varun Agrawal ,  John Kalamatianos

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0653 ,  G06F3/0679 ,  G06F3/0604

    Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.

    FLEXIBLE DICTIONARY SHARING FOR COMPRESSED CACHES
    124.
    发明公开
    FLEXIBLE DICTIONARY SHARING FOR COMPRESSED CACHES 审中-公开

    公开(公告)号：US20230161710A1

    公开(公告)日：2023-05-25

    申请号：US18158212

    申请日：2023-01-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander D. Breslow ,  John Kalamatianos

    IPC: G06F12/0895 ,  H03M7/30

    CPC classification number: G06F12/0895 ,  H03M7/3088 ,  G06F2212/1044 ,  G06F2212/608

    Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

    Address-based filtering for load/store speculation
    125.
    发明授权
    Address-based filtering for load/store speculation 有权

    公开(公告)号：US11645073B2

    公开(公告)日：2023-05-09

    申请号：US17238844

    申请日：2021-04-23

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Kalamatianos ,  Krishnan V. Ramani ,  Susumu Mashimo

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/35

    CPC classification number: G06F9/30043 ,  G06F9/35 ,  G06F9/3842

    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.

    GPU cache management based on locality type detection
    126.
    发明授权
    GPU cache management based on locality type detection 有权

    公开(公告)号：US11487671B2

    公开(公告)日：2022-11-01

    申请号：US16446119

    申请日：2019-06-19

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Xianwei Zhang ,  John Kalamatianos ,  Bradford Beckmann

    IPC: G06F12/0891 ,  G06F12/0888 ,  G06F12/0895 ,  G06F9/54 ,  G06F9/38

    Abstract: Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.

    Controlling prediction functional blocks used by a branch predictor in a processor
    127.
    发明授权
    Controlling prediction functional blocks used by a branch predictor in a processor 有权

    公开(公告)号：US11442727B2

    公开(公告)日：2022-09-13

    申请号：US16895825

    申请日：2020-06-08

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Varun Agrawal ,  John Kalamatianos

    IPC: G06F9/44 ,  G06F9/30 ,  G06F9/38

    Abstract: An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

    SEMI-SORTING COMPRESSION WITH ENCODING AND DECODING TABLES
    128.
    发明申请
    SEMI-SORTING COMPRESSION WITH ENCODING AND DECODING TABLES 有权

    公开(公告)号：US20220239315A1

    公开(公告)日：2022-07-28

    申请号：US17722931

    申请日：2022-04-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander D. Breslow ,  Nuwan Jayasena ,  John Kalamatianos

    IPC: H03M7/40 ,  G06F7/08 ,  G06F3/06

    Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.

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