公开(公告)号：US5434514A

公开(公告)日：1995-07-18

申请号：US979003

申请日：1992-11-19

申请人： Richard G. Cliff ,  Rina Raman ,  Srinivas T. Reddy

发明人： Richard G. Cliff ,  Rina Raman ,  Srinivas T. Reddy

IPC分类号： H01L21/82 ,  G06F11/20 ,  H03K19/003 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  H03K19/00392

摘要： A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.

摘要翻译： 可编程的集成电路逻辑阵列器件具有多个常规逻辑组和至少一个备用逻辑组。 如果任何常规逻辑组有故障，则备用逻辑组用于弥补故障逻辑组。 为了实现这一点，通常去故障逻辑组的编程和数据输入信号被重定向到另一个逻辑组。 另一组的数据输出信号代替通常已经接收到编程的逻辑组的数据输出信号和被重定向到另一个逻辑组的数据输入信号。

公开(公告)号：US5237219A

公开(公告)日：1993-08-17

申请号：US880908

申请日：1992-05-08

申请人： Richard G. Cliff

发明人： Richard G. Cliff

IPC分类号： G05B19/05 ,  G01R31/3185 ,  G06F9/06 ,  H03K19/173 ,  H03K19/177

CPC分类号： G01R31/318519

摘要： In order to simplify the programming structure and facilitate testing of that structure, the programmable elements in a cellular programmable logic integrated circuit (such as a field programmable gate array ("FPGA") or a programmable logic device ("PLD")) are connected in one or more series with switches interposed between the elements in the series. Initially, all of the switches in each series are enabled so that the ability of the series to correctly pass data can be tested. Thereafter, the switches are progressively disabled, starting from the switch which is most remote from the data source, so that data is stored in successive programmable elements, again starting with the programmable element which is most remote from the data source.

公开(公告)号：US08542042B1

公开(公告)日：2013-09-24

申请号：US13532528

申请日：2012-06-25

申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

IPC分类号： H03L7/06

CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

摘要： One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种可断裂的PLL电路。 断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。 可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。 另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。 可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。 还公开了其它实施例和特征。

公开(公告)号：US20100277201A1

公开(公告)日：2010-11-04

申请号：US12434606

申请日：2009-05-01

申请人： Curt Wortman ,  Chong H. Lee ,  Richard G. Cliff

发明人： Curt Wortman ,  Chong H. Lee ,  Richard G. Cliff

IPC分类号： H03K19/173 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/84 ,  H03K19/17724 ,  H03K19/17732

摘要： An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.

摘要翻译： 提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。 第二区包括标准逻辑单元和基本单元。 在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。 基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。 在一个实施例中，第二区域可以嵌入第一区域。 在另一个实施例中，第二区域围绕第一区域的周边限定。 可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。 在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用40G / 100G替换用于基于计算的应用的诸如PCI Express的原始功能 以太网和因特拉肯，用于有线应用。 还提供了一种设计集成电路的方法。

公开(公告)号：US06977520B1

公开(公告)日：2005-12-20

申请号：US10219085

申请日：2002-08-13

申请人： Michael D. Hutton ,  Richard G. Cliff

发明人： Michael D. Hutton ,  Richard G. Cliff

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17792

摘要： Programmable logic device interconnection resources include bus wires. A bus wire provides a programmable signal path across the programmable logic device from several logic device outputs to several other logic device inputs.Serializing circuitry multiplexes multiple device output signals and drives time-multiplexed data signals on the bus wires. Bus registers placed at the ends of bus wires register or buffer the data signals transmitted over the bus wires. The registered signals are passed on to deserializing circuitry for demultiplexing data signals to provide parallel device input signals. The bus registers, and the serializing/deserializing circuitry are clocked at a rate faster than the device system clock to schedule the use of the bus wires for transmission of multiple device input/output signals over the bus wires within a system clock cycle.

摘要翻译： 可编程逻辑器件互连资源包括母线。 总线线路将可编程逻辑器件的可编程信号路径从若干逻辑器件输出提供给其他几个逻辑器件输入。 串行化电路复用多个器件输出信号并在总线上驱动时间复用数据信号。 布置在总线末端的总线寄存器寄存或缓冲通过总线发送的数据信号。 注册的信号被传递到用于解复用数据信号的反序列化电路以提供并行设备输入信号。 总线寄存器和序列化/反序列化电路以比器件系统时钟速度更快的速度进行计时，以调度在系统时钟周期内通过总线传输多个器件输入/输出信号的总线线路。

公开(公告)号：US06798242B2

公开(公告)日：2004-09-28

申请号：US10426991

申请日：2003-04-29

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US06681378B2

公开(公告)日：2004-01-20

申请号：US10175980

申请日：2002-06-19

申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

IPC分类号： G06F1750

CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

公开(公告)号：US06646467B1

公开(公告)日：2003-11-11

申请号：US10147200

申请日：2002-05-17

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pendersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pendersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19177

CPC分类号： H03K19/1774 ,  H03K19/17744

摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.

摘要翻译： 可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。 设备上的一些寄存器紧密耦合，用于数据输入和输出到器件的数据信号输入/输出引脚。 至少这些寄存器的时钟信号输入端也紧密耦合到器件的时钟信号输入引脚。 在数据信号输入/输出引脚和上述寄存器的数据输入端之间提供可编程输入延迟，以帮助补偿器件上的时钟信号偏移。

公开(公告)号：US06577160B2

公开(公告)日：2003-06-10

申请号：US10170026

申请日：2002-06-10

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联。 本地导体与每个区域相关联。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US06483886B1

公开(公告)日：2002-11-19

申请号：US09366940

申请日：1999-08-04

申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Richard G. Cliff

发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Richard G. Cliff

IPC分类号： H03L706

CPC分类号： H03K19/1774 ,  H03K19/177 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/183

摘要： A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.

摘要翻译： 锁相环电路（“PLL”）可在相位和频率两个方面调节。 通过在PLL的压控振荡器上提供多个抽头，并提供单独的多路复用器，每个复用器可以为PLL反馈回路选择不同的抽头，并为PLL输出选择一个，一个允许用户调整 输出的相位相对于输入的相位。 类似地，通过提供可加载的预缩放（除以N），后标尺（除以K）和反馈量表（除以M）计数器，允许用户将输出的频率调整为M /（NK ）倍的输入。