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121.发明授权Electrical critical dimension measurement and defect detection for reticle fabrication 失效电子临界尺寸测量和掩模版制作的缺陷检测公开(公告)号：US06972576B1
公开(公告)日：2005-12-06
申请号：US10160334
申请日：2002-05-31
IPC分类号： G01R27/08 , G03F1/00 , G03F1/14 , H01L23/544
摘要： A system for testing a reticle used in semiconductor wafer fabrication is provided. The system includes a reticle that has an opaque metal layer over a translucent substrate. The reticle includes one or more test features containing probe points operable for electrical contact. The system includes a reticle test system that is capable of applying a voltage to the probe points, measuring the resulting current, calculating the corresponding resistance of the test features, and determining the critical dimensions of the test features. The system is also capable of determining defects based on the resistance measurements. The critical dimension information and defect information can then be used to refine the processes used in the fabrication of subsequent reticles.
摘要翻译： 提供了一种用于半导体晶片制造中使用的掩模版的测试系统。 该系统包括在半透明基底上具有不透明金属层的掩模版。 掩模版包括一个或多个测试特征，其中包含可操作用于电接触的探针点。 该系统包括能够对探针点施加电压，测量所得电流，计算相应的测试特征的电阻以及确定测试特征的临界尺寸的光罩测试系统。 该系统还能够基于电阻测量来确定缺陷。 关键尺寸信息和缺陷信息随后可被用于改进在随后的掩模版的制造中使用的工艺。
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公开(公告)号：US06906777B1
公开(公告)日：2005-06-14
申请号：US10790412
申请日：2004-03-01
CPC分类号： G03F7/70983 , G03F7/70833 , G03F7/70916
摘要： A method and apparatus for preventing contamination in a lithographic apparatus including a projection system, including providing the lithographic apparatus including the projection system for imaging an irradiated portion of a mask onto a target portion of a substrate and placing a pellicle over a surface of the projection system to inhibit contamination of the surface.
摘要翻译： 一种用于防止在包括投影系统的光刻设备中的污染的方法和设备，包括提供包括投影系统的光刻设备，用于将掩模的照射部分成像到基板的目标部分上，并将防护薄膜组件放置在突出部分的表面上 系统抑制表面的污染。
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公开(公告)号：US06836398B1
公开(公告)日：2004-12-28
申请号：US10284769
申请日：2002-10-31
申请人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
发明人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01G435
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L21/3212 , H01L27/285 , H01L28/75
摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
摘要翻译： 本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。 本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。 在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。 还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。 因此，钝化层与用于形成电极的还原CMP工艺结合形成。
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公开(公告)号：US06771356B1
公开(公告)日：2004-08-03
申请号：US10050626
申请日：2002-01-16
申请人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
发明人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
IPC分类号： G01B1116
CPC分类号： G01B11/165
摘要： A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.
摘要翻译： 提供了一种用于监视制造工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个光栅。 从光栅反射的光被处理收集的光的测量系统收集。 所收集的光指示由于晶片的各个部分处的应力引起的变形。 测量系统向处理器提供失真/应力相关数据，该处理器确定晶片各部分的失真的可接受性。 收集的光可以通过散射测量系统进行分析，以产生与失真相关联的散射仪签名并产生可用于控制半导体制造过程的前馈控制信息。
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公开(公告)号：US06686270B1
公开(公告)日：2004-02-03
申请号：US10212983
申请日：2002-08-05
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76813 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.
摘要翻译： 本发明的一个方面涉及一种双镶嵌加工方法，包括在绝缘结构中形成多个通孔，该绝缘结构包含单层电介质材料; 并且（i）在所述绝缘结构中形成多个沟槽，每个沟槽沿着一组通孔开口的基本直线定位，以及（ii）使用散射测量系统监测沟槽的形成以确定沟槽深度，并且终止 当获得所需的沟槽深度时形成沟槽。
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126.发明授权公开(公告)号：US06654659B1
公开(公告)日：2003-11-25
申请号：US10178084
申请日：2002-06-24
IPC分类号： G06F1900
CPC分类号： H01L21/67253 , H01L21/67063 , H01L22/20
摘要： One aspect of the present invention relates to a feedback-driven, closed loop system/method for obtaining consistently formed semiconductor structures. The system/method involves controlling the progression of a lithography process such as a deposition or etching process. The system employs one or more piezoelectric sensors, such as quartz crystal sensors, integrated on a wafer. During the lithography process, the sensors produce frequency data which is analyzed and communicated to a lithography process controller in order to modulate one or more process parameters and/or one or more process components. The frequency data indicates the progression of the lithography process and facilitates determining whether the parameters/components need correction to obtain structures which are consistent throughout the wafer and from wafer to wafer. Data generated by each sensor located at an area on the wafer may be cross-referenced with data from other sensors on the wafer and with data from other wafers to ensure uniformity and consistency among the wafers.
摘要翻译： 本发明的一个方面涉及一种用于获得一致形成的半导体结构的反馈驱动的闭环系统/方法。 该系统/方法涉及控制诸如沉积或蚀刻工艺的光刻工艺的进展。 该系统采用集成在晶片上的一个或多个压电传感器，例如石英晶体传感器。 在光刻过程期间，传感器产生频率数据，其被分析并传送到光刻过程控制器，以便调制一个或多个过程参数和/或一个或多个过程组件。 频率数据指示光刻过程的进展，并且有助于确定参数/组件是否需要校正以获得在整个晶片和晶片与晶片之间一致的结构。 由位于晶片上的每个传感器生成的数据可以与来自晶片上的其他传感器的数据和来自其他晶片的数据进行交叉参考，以确保晶片之间的均匀性和一致性。
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公开(公告)号：US06624642B1
公开(公告)日：2003-09-23
申请号：US10016252
申请日：2001-12-10
IPC分类号： G01R2700
CPC分类号： H01L21/3212 , H01L21/32051 , H01L21/32136 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
摘要翻译： 公开了一种包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层，以及至少一个嵌入在晶片中和晶片中的至少一个的电传感器，以促进金属层在其进行时的实时监测 减色金属化工艺。 该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动 从电传感器检测和接收，用于实时监测减色金属化处理。
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公开(公告)号：US06589711B1
公开(公告)日：2003-07-08
申请号：US09824696
申请日：2001-04-04
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.
摘要翻译： 提供了在第一层中制作双重嵌入通孔的方法。 第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。 该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成双层抗蚀剂。 双层抗蚀剂包括底部抗反射涂层（BARC）上方的成像层。 成像层选择性地暴露于辐射，使得在通过BARC的上部的第一开口中没有辐射到达BARC的下部。 双层抗蚀剂被图案化，并且使用图案化双层抗蚀剂作为掩模，形成与第一开口连通的第二开口，例如沟槽。
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129.发明授权公开(公告)号：US06423475B1
公开(公告)日：2002-07-23
申请号：US09266367
申请日：1999-03-11
IPC分类号： G03C500
CPC分类号： H01L21/32139
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a photoresist over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the photoresist having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the photoresist, the sidewall film having a vertical portion adjacent the sidewall of the photoresist and a horizontal portion in areas not adjacent the sidewall of the photoresist; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the photoresist exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译： 在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化光致抗蚀剂，其中所述导电膜的第二部分被暴露，所述光致抗蚀剂在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述光致抗蚀剂上沉积侧壁膜，所述侧壁膜具有邻近所述光致抗蚀剂的侧壁的垂直部分和在不邻近所述光致抗蚀剂的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的光致抗蚀剂; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。
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公开(公告)号：US06403456B1
公开(公告)日：2002-06-11
申请号：US09643611
申请日：2000-08-22
IPC分类号： H01L2128
CPC分类号： H01L29/42376 , H01L21/28114 , H01L21/28123 , H01L21/76802
摘要： A method for fabricating a T-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. A photoresist layer is formed over the second sacrificial layer. An opening is formed in the photoresist layer. An opening is then formed in the second sacrificial layer beneath the opening in the photoresist layer. The opening is then expanded in the photoresist layer to expose portions of the top surface of the second sacrificial layer around the opening in the second sacrificial layer. The opening is extended in the second sacrificial layer through the first sacrificial layer and the opening is expanded in the second sacrificial layer to form a T-shaped opening in the first and second sacrificial layers. The photoresist layer is removed and the T-shaped opening is filled with a conductive material.
摘要翻译： 提供了一种制造T型栅结构的方法。 该方法包括以下步骤：提供具有栅极氧化物层的硅层，栅极氧化物层上的保护层，保护层上的第一牺牲层和第一牺牲层上的第二牺牲层。 在第二牺牲层上形成光致抗蚀剂层。 在光致抗蚀剂层中形成开口。 然后在光致抗蚀剂层中的开口下方的第二牺牲层中形成开口。 然后在光致抗蚀剂层中扩展开口，以暴露第二牺牲层的顶表面的部分围绕第二牺牲层中的开口。 所述开口在所述第二牺牲层中延伸穿过所述第一牺牲层，并且所述开口在所述第二牺牲层中膨胀以在所述第一和第二牺牲层中形成T形开口。 去除光致抗蚀剂层，并用导电材料填充T形开口。
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