公开(公告)号：US11764452B2

公开(公告)日：2023-09-19

申请号：US17672876

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan

IPC: H01P3/16 ,  H01L23/66 ,  H01P11/00 ,  H04B10/2581

CPC classification number: H01P3/16 ,  H01L23/66 ,  H01P11/006 ,  H01L2223/6627 ,  H04B10/2581

Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.

公开(公告)号：US11694962B2

公开(公告)日：2023-07-04

申请号：US17229991

申请日：2021-04-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

CPC classification number: H01L23/5385 ,  B81B7/0006 ,  B81B7/007 ,  H01L21/565 ,  H01L23/28 ,  H01L23/5384 ,  H01L23/552

Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.

公开(公告)号：US20230197620A1

公开(公告)日：2023-06-22

申请号：US17558304

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Neelam Prabhu Gaunkar ,  Brandon Rawlings

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49866

Abstract: Methods, systems, apparatus, and articles of manufacture are disclosed for integrated circuit package substrates with high aspect ratio through glass vias. An example microelectronic package including a glass substrate including a via, the via including a high aspect ratio. The example microelectronic package further including a seed layer extending substantially evenly along an inner wall of the via.

公开(公告)号：US11641711B2

公开(公告)日：2023-05-02

申请号：US17695118

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/12 ,  H05K3/40 ,  H05K9/00

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11621192B2

公开(公告)日：2023-04-04

申请号：US17338296

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.

公开(公告)号：US11532574B2

公开(公告)日：2022-12-20

申请号：US16394905

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L21/00 ,  H01L23/66 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01P3/16 ,  H01P3/06 ,  H01P11/00

Abstract: Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US20220399294A1

公开(公告)日：2022-12-15

申请号：US17347394

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Adel A. Elsherbini ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

公开(公告)号：US20220201843A1

公开(公告)日：2022-06-23

申请号：US17695118

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/12 ,  H05K3/40 ,  H05K9/00

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11367937B2

公开(公告)日：2022-06-21

申请号：US16464673

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Telesphor Kamgaing

IPC: H01P3/16 ,  H01P3/08 ,  H03F3/19 ,  H03H11/04 ,  H05K1/02 ,  H05K1/18 ,  H05K7/14

Abstract: Embodiments of the invention may include a mm-wave waveguide. In an embodiment, the mm-wave waveguide may include a first dielectric waveguide and a second dielectric waveguide. A conductive layer may be used to cover the first dielectric waveguide and the second dielectric waveguide in some embodiments. Furthermore, embodiments may include a repeater communicatively coupled between the first dielectric waveguide and the second dielectric waveguide. In an embodiment, the repeater may be an active repeater or a passive repeater. According to an embodiment, a passive repeater may be integrated within the dielectric waveguide. The passive repeater may include a dispersion compensating material that produces a dispersion response in a signal that is substantially opposite to a dispersion response produced when the signal is propagated along the dielectric waveguide.

公开(公告)号：US11309619B2

公开(公告)日：2022-04-19

申请号：US16327811

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： Sasha Oster ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  Johanna Swan

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q21/06 ,  H01Q21/00 ,  H01P5/18

Abstract: A waveguide coupling system may include at least one waveguide member retention structure disposed on an exterior surface of a semiconductor package. The waveguide member retention structure may be disposed a defined distance or at a defined location with respect to an antenna carried by the semiconductor package. The waveguide member retention structure may engage and guide a waveguide member slidably inserted into the respective waveguide member retention structure. The waveguide member retention structure may position the waveguide member at a defined location with respect to the antenna to maximize the power transfer from the antenna to the waveguide member.