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121.发明申请SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING 有权具有拉伸和/或压缩应力的半导体器件及其制造方法公开(公告)号：US20090206407A1
公开(公告)日：2009-08-20
申请号：US12033280
申请日：2008-02-19
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译： 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。
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122.发明申请TRANSISTOR HAVING GATE AND BODY IN DIRECT SELF-ALIGNED CONTACT AND RELATED METHODS 失效在直接自对准接触中具有门和体的晶体管和相关方法公开(公告)号：US20080217707A1
公开(公告)日：2008-09-11
申请号：US11683470
申请日：2007-03-08
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78615 , H01L29/783
摘要： A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. One method may include providing the body; forming a sacrificial layer that contacts at least a portion of a sidewall of the body; forming a dielectric layer about the body except at the at least a portion; removing the sacrificial layer; and forming the gate about the body such that the gate contacts the at least a portion of the sidewall of the body.
摘要翻译： 公开了一种具有直接接触门和体的晶体管及相关方法。 在一个实施例中，晶体管包括栅极; 身体; 以及电介质层，其延伸到所述主体上，以沿着所述主体的至少一个侧壁的一部分沿着所述主体的整个表面使所述门与所述主体绝缘，其中所述门在所述部分处与所述主体直接接触。 一种方法可以包括提供身体; 形成与身体的侧壁的至少一部分接触的牺牲层; 在所述至少一部分之外形成围绕所述主体的介电层; 去除牺牲层; 以及围绕所述主体形成所述门，使得所述门接触所述主体的侧壁的至少一部分。
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123.发明申请TRANSISTOR HAVING SOURCE/DRAIN REGION ONLY UNDER SIDEWALL SPACER EXCEPT FOR CONTACTS AND METHOD 审中-公开具有源/漏区的晶体管仅在接线端子和方法之外公开(公告)号：US20080122010A1
公开(公告)日：2008-05-29
申请号：US11555826
申请日：2006-11-02
CPC分类号： H01L27/1203 , H01L21/823418 , H01L21/823468 , H01L21/84 , H01L29/66636 , H01L29/66772 , H01L29/78618
摘要： A transistor and related method are disclosed. The transistor may include a gate, a sidewall spacer formed along the gate, and a source/drain region positioned only under the sidewall spacer except for a portion at which a contact is positioned. The transistor may be ultra-low power and sub-threshold voltage or near sub-threshold voltage. The transistor may exhibit at least two times reduction in outer fringe capacitance (Cof).
摘要翻译： 公开了一种晶体管及相关方法。 晶体管可以包括栅极，沿着栅极形成的侧壁隔离物，以及仅位于侧壁隔板之下的源极/漏极区域，除了接触位置的部分之外。 晶体管可能是超低功耗和次阈值电压或接近亚阈值电压。 晶体管可以表现出外边缘电容（C SUB）的至少两倍的降低。
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公开(公告)号：US07326976B2
公开(公告)日：2008-02-05
申请号：US11164216
申请日：2005-11-15
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.
摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。
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公开(公告)号：US07736053B2
公开(公告)日：2010-06-15
申请号：US12348974
申请日：2009-01-06
摘要： Disclosed are embodiments of an improved on-chip temperature sensing circuit, based on bolometry, which provides self calibration of the on-chip temperature sensors for ideality and an associated method of sensing temperature at a specific on-chip location. The circuit comprises a temperature sensor, an identical reference sensor with a thermally coupled heater and a comparator. The comparator is adapted to receive and compare the outputs from both the temperature and reference sensors and to drive the heater with current until the outputs match. Based on the current forced into the heater, the temperature rise of the reference sensor can be calculated, which in this state, is equal to that of the temperature sensor.
摘要翻译： 公开了一种改进的片上温度感测电路的实施例，其基于速率测量，其提供用于理想的片上温度传感器的自校准以及在特定片上位置处感测温度的相关联的方法。 该电路包括温度传感器，具有热耦合加热器的相同参考传感器和比较器。 比较器适用于接收和比较来自温度和参考传感器的输出，并用电流驱动加热器直到输出匹配。 基于被迫进入加热器的电流，可以计算参考传感器的温度上升，在该状态下，其温度上升等于温度传感器的温升。
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126.发明申请SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE 有权具有现场屏蔽的半导体结构和形成结构的方法公开(公告)号：US20100047972A1
公开(公告)日：2010-02-25
申请号：US12610563
申请日：2009-11-02
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L29/861 , H01L29/402 , H01L29/417 , H01L29/6609 , H01L29/772 , H01L29/78648
摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.
摘要翻译： 公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。 场屏蔽被夹在晶片上的上隔离层和下隔离层之间。 局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。 进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。 因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。 该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。
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127.发明授权Circuit to compensate threshold voltage variation due to process variation 失效用于补偿由于过程变化引起的阈值电压变化的电路公开(公告)号：US07667527B2
公开(公告)日：2010-02-23
申请号：US11561480
申请日：2006-11-20
IPC分类号： H03K3/01
CPC分类号： G05F3/205
摘要： Structure and process for compensating threshold voltage variation due to process variation. The structure includes a circuit segmented into sub-blocks having a predetermined size corresponding to a characteristic length associated with a process variation. A local circuit is located in each circuit sub-block, and a reference signal coupled to each local circuit. The local circuit generates a compensation signal in response to the reference signal to adjust an electrical parameter of the respective sub-block to a predetermined value.
摘要翻译： 用于补偿由于过程变化引起的阈值电压变化的结构和过程。 该结构包括分割成具有对应于与过程变化相关联的特征长度的预定尺寸的子块的电路。 本地电路位于每个电路子块中，并且参考信号耦合到每个本地电路。 本地电路响应于参考信号产生补偿信号，以将相应子块的电参数调整到预定值。
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公开(公告)号：US07378357B2
公开(公告)日：2008-05-27
申请号：US11264446
申请日：2005-11-01
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/66818
摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
摘要翻译： 公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。 这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。 较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。 包括与栅极电介质不同的材料的盖可以位于鳍片上方。
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公开(公告)号：US06469350B1
公开(公告)日：2002-10-22
申请号：US09682868
申请日：2001-10-26
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/743 , H01L29/66545 , H01L29/78612 , H01L29/78618 , Y10S148/077 , Y10S148/15
摘要： A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.
摘要翻译： 本文公开了在绝缘体上硅衬底上制造并具有活性阱方案的半导体器件以及制造这种器件的包括非自对准和自对准的方法。 半导体器件包括至少包括体区127和扩散区132的场效应晶体管124; 埋入的互连平面122可选地与扩散区132自对准并与体区127接触; 扩散区域132和掩埋互连平面122之间的隔离氧化物区域118; 和掩埋的互连平面122下方的掩埋氧化物层104。
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公开(公告)号：US07932134B2
公开(公告)日：2011-04-26
申请号：US12610563
申请日：2009-11-02
CPC分类号： H01L29/861 , H01L29/402 , H01L29/417 , H01L29/6609 , H01L29/772 , H01L29/78648
摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.
摘要翻译： 公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。 场屏蔽被夹在晶片上的上隔离层和下隔离层之间。 局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。 进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。 因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。 该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。
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