公开(公告)号：US20090127595A1

公开(公告)日：2009-05-21

申请号：US12127850

申请日：2008-05-28

申请人： William F. Clark, JR. ,  Edward J. Nowak

发明人： William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L29/772 ,  H01L23/48 ,  H01L21/762 ,  H01L21/8232

CPC分类号： H01L29/861 ,  H01L29/402 ,  H01L29/417 ,  H01L29/6609 ,  H01L29/772 ,  H01L29/78648

摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate

摘要翻译： 公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。 场屏蔽被夹在晶片上的上隔离层和下隔离层之间。 局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。 进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。 因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。 该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障

公开(公告)号：US20090096026A1

公开(公告)日：2009-04-16

申请号：US11872953

申请日：2007-10-16

申请人： Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78624 ,  H01L29/66772 ,  H01L29/78612

摘要： A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI.

摘要翻译： 一种制造高电压完全耗尽的绝缘体上硅（FD SOI）晶体管的方法，所述FD SOI晶体管具有包括在其中设置栅极结构的主体内的区域的结构。 该区域包括分离源极区域和漏极区域的沟道。 在源极区上方设置有载流子复合元件，该载流子复合元件邻接栅极结构，并且经由沟道电连接到该区域。 漏极区域被轻掺杂并镇流以增加击穿电压。 可以通过形成具有设置在掩埋氧化物（BOX）上的薄硅层的主体来制造FD SOI。 或者，可以使用部分耗尽（PD）SOI形成主体，其中形成在其中的区域与PD SOI的总厚度相比具有减小的厚度。

公开(公告)号：US20110101449A1

公开(公告)日：2011-05-05

申请号：US12985060

申请日：2011-01-05

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

公开(公告)号：US20090119626A1

公开(公告)日：2009-05-07

申请号：US11935612

申请日：2007-11-06

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： G06F17/50

CPC分类号： H01L29/78615

摘要： A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion.

摘要翻译： 公开了一种包括具有直接接触的栅极和主体的晶体管的设计结构。 在一个实施例中，晶体管包括栅极; 身体; 以及电介质层，其延伸到所述主体上，以沿着所述主体的至少一个侧壁的一部分沿着所述主体的整个表面使所述门与所述主体绝缘，其中所述门在所述部分处与所述主体直接接触。

公开(公告)号：US20120211854A1

公开(公告)日：2012-08-23

申请号：US13029670

申请日：2011-02-17

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/0352 ,  G06F17/50 ,  H01L31/18

CPC分类号： H01L27/14614

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

公开(公告)号：US20090020830A1

公开(公告)日：2009-01-22

申请号：US11869145

申请日：2007-10-09

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

摘要： Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

摘要翻译： 公开了用于非对称场效应晶体管结构的设计结构的实施例以及形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（ 即，以最小的电路延迟来提供改进的驱动电流）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

公开(公告)号：US20120301990A1

公开(公告)日：2012-11-29

申请号：US13571986

申请日：2012-08-10

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/18

CPC分类号： H01L27/14614

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

公开(公告)号：US20120235216A1

公开(公告)日：2012-09-20

申请号：US13051510

申请日：2011-03-18

申请人： Brent A. ANDERSON ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. ANDERSON ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/0216 ,  G06F17/50 ,  H01L31/18

CPC分类号： H01L31/0232 ,  G06F17/5045 ,  G06F17/5054 ,  H01L27/14632 ,  H01L27/14683 ,  H01L29/66545

摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.

摘要翻译： 提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。 该方法包括在虚拟栅极结构上形成介电层。 该方法还包括在电介质层中形成一个或多个凹槽。 该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。 该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

公开(公告)号：US20120168832A1

公开(公告)日：2012-07-05

申请号：US13246175

申请日：2011-09-27

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

公开(公告)号：US20090261415A1

公开(公告)日：2009-10-22

申请号：US12104683

申请日：2008-04-17

申请人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L49/00 ,  H01L21/00

CPC分类号： H01L29/78603 ,  H01L29/66621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

摘要翻译： 公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流 区域和源极区域和/或用于改变阈值电压。 这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。 还公开了用于形成这种FET的方法实施例。