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    Read Channel Sampling Utilizing Two Quantization Modules for Increased Sample Bit Width
    121.
    发明申请
    Read Channel Sampling Utilizing Two Quantization Modules for Increased Sample Bit Width 有权
    读取通道采样利用两个量化模块增加采样位宽度

    公开(公告)号：US20150228303A1

    公开(公告)日：2015-08-13

    申请号：US14198008

    申请日：2014-03-05

    Applicant: LSI Corporation

    Inventor： Xuebin Wu ,  Yang Han ,  Weijun Tan ,  Shaohua Yang

    IPC: G11B20/10

    CPC classification number: G11B20/10046 ,  G10L19/0208 ,  G11B5/012 ,  G11B5/5526 ,  G11B5/553 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/1403

    Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

    Abstract translation: 公开了一种由这种通信信道结构支持的通信信道结构和解码方法。 这样的通信信道包括被配置为对输入信号进行滤波的数字滤波器和被配置为量化滤波信号的两个量化器。 利用第一量化器来量化滤波后的信号以产生具有第一精度的第一量化样本，并且使用第二量化器量化滤波信号以产生具有第二精度的第二量化样本，其中第二精度不同于 第一精度。 通信信道还包括迭代解码器，其被配置为利用第一量化样本进行解码过程的第一全局迭代，并且利用第二量化样本进行解码过程的至少一个后续全局迭代。

    Zero Phase Start Estimation in Readback Signals
    122.
    发明申请
    Zero Phase Start Estimation in Readback Signals 有权
    回读信号中的零相位开始估计

    公开(公告)号：US20150228302A1

    公开(公告)日：2015-08-13

    申请号：US14197748

    申请日：2014-03-05

    Applicant: LSI Corporation

    Inventor： Xuebin Wu ,  Shaohua Yang ,  Zhi Bin Li ,  Haitao Xia

    IPC: G11B20/10

    CPC classification number: G11B20/1024 ,  G11B20/10037

    Abstract: A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.

    Abstract translation: 数据存储系统识别幅度低于某一阈值的模数转换样本。 剩余样品根据阶段分组成一个或多个象限。 使用具有重叠象限的多坐标来进一步区分采样点。 然后，该系统计算零相位开始估计的平均相位。

    Slice Formatting and Interleaving for Interleaved Sectors
    124.
    发明申请
    Slice Formatting and Interleaving for Interleaved Sectors 有权
    切片扇区的切片格式和交错

    公开(公告)号：US20150161045A1

    公开(公告)日：2015-06-11

    申请号：US14153154

    申请日：2014-01-13

    Applicant: LSI Corporation

    Inventor： Qi Zuo ,  Kuhong Jeong ,  Shu Li ,  Xiang Wang ,  Han Fang ,  Shaohua Yang

    IPC: G06F12/06

    CPC classification number: G06F12/0607

    Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.

    Abstract translation: 公开了一种用于在存储系统中交织多个逻辑扇区的存储系统和方法。 该方法包括：将每个逻辑扇区划分成预定数量的片; 顺序索引逻辑扇区，其中每个逻辑扇区由逻辑扇区索引标识; 顺序索引每个逻辑扇区中的预定数量的片，其中预定数量片的每个片由每个逻辑扇区内的片索引识别; 以及根据片交织处理对逻辑扇区进行交织。 交错步骤还包括：a）将第一索引逻辑扇区的第一索引片段识别为初始片段; 以及b）通过将切片索引推进到切片索引序列中的后续索引并且将逻辑扇区索引推进到逻辑扇区索引序列中的后续索引来识别随后的片段。

    System and method for power saving modes in multi-sensor magnetic recording
    127.
    发明授权
    System and method for power saving modes in multi-sensor magnetic recording 有权
    多传感器磁记录中省电模式的系统和方法

    公开(公告)号：US09001446B1

    公开(公告)日：2015-04-07

    申请号：US14194069

    申请日：2014-02-28

    Applicant: LSI Corporation

    Inventor： Bruce A. Wilson ,  Richard Rauschmayer ,  Peter J. Windler ,  Jefferson E. Singleton ,  Shaohua Yang ,  Jeffrey P. Grundvig

    IPC: G11B5/09 ,  G11B5/596 ,  G11B20/10

    CPC classification number: G11B5/59616 ,  G11B5/09 ,  G11B19/00 ,  G11B20/10037 ,  G11B2005/0008

    Abstract: A system and method for power management in a hard disk drive (HDD) assembly incorporating two or more read sensors includes directing a read/write head to follow a track; depowering one or more read sensors and readpath circuits associated with the read sensors; reading an analog readback signal through the first read sensor; processing the signal through an analog front-end to generate an input signal; sampling the input signal through an analog to digital converter at a first frequency to generate a first sampling signal; sampling the input signal through a second analog to digital converter at a second frequency to generate a second sampling signal; and generating a digital output signal from either or both sampling signals at a third sampling frequency through a digital signal processor. The method may additionally comprise adjusting a sampling frequency when power level reaches a threshold.

    Abstract translation: 包含两个或更多个读取传感器的硬盘驱动器（HDD）组件中的电源管理的系统和方法包括引导读/写头跟随轨道; 降低与读取的传感器相关联的一个或多个读取传感器和读取路径电路; 通过第一个读取传感器读取模拟回读信号; 通过模拟前端处理信号以产生输入信号; 以第一频率通过模数转换器对输入信号进行采样，以产生第一采样信号; 以第二频率通过第二模数转换器对输入信号进行采样，以产生第二采样信号; 以及通过数字信号处理器以第三采样频率从一个或两个采样信号产生数字输出信号。 该方法还可以包括当功率电平达到阈值时调整采样频率。

    Systems and methods for distributed low density parity check decoding
    128.
    发明授权
    Systems and methods for distributed low density parity check decoding 有权
    分布式低密度奇偶校验解码的系统和方法

    公开(公告)号：US08930792B2

    公开(公告)日：2015-01-06

    申请号：US13766891

    申请日：2013-02-14

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Shaohua Yang ,  Zongwang Li ,  Yang Han

    IPC: H03M13/00 ,  H03M13/13 ,  H03M13/29 ,  G11B20/18 ,  H04L1/00

    CPC classification number: H03M13/13 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/2978 ,  H03M13/6325 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于利用多个数据流进行数据从存储设备的数据恢复的系统和方法。 在一些情况下，系统包括低密度奇偶校验数据解码器电路，其包括至少第一数据解码器引擎和第二数据解码器引擎，每个电耦合到公共电路。 公共电路可操作用于：将来自第一数据解码器引擎的第一子消息和来自第二数据解码器引擎的第二子消息的组合移位以产生移位的输出，并且分解转移的输出以产生第三 子消息发送到第一数据解码器引擎，第四子消息发送到第二解码器引擎。

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