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    ERASING MEMORY
    121.
    发明申请
    ERASING MEMORY 有权

    公开(公告)号：US20230078036A1

    公开(公告)日：2023-03-16

    申请号：US17988090

    申请日：2022-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

    Memory device including data lines on multiple device levels
    122.
    发明授权
    Memory device including data lines on multiple device levels 有权

    公开(公告)号：US11605588B2

    公开(公告)日：2023-03-14

    申请号：US16723758

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Paolo Tessariol ,  Aaron Yip ,  Naveen Kaushik

    IPC: H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first pillar of a first memory cell string; a second pillar of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure located over and in electrical contact with the first pillar; a second conductive structure extending in the first direction, the second conductive structure located over and in electrical contact with the second pillar; a select gate coupled to the first and second memory cell strings; a first data line located on a first level of the apparatus and extending in a second direction, the first data line located over the first conductive structure and in electrical contact with the first conductive structure; and a second data line located on a second level of the apparatus and extending in the second direction, the second data line located over the second conductive structure and in electrical contact with the second conductive structure.

    MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    124.
    发明申请
    MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220392914A1

    公开(公告)日：2022-12-08

    申请号：US17819009

    申请日：2022-08-11

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Maria Meotto ,  Emilio Camerlenghi ,  Paolo Tessariol ,  Luca Laurin

    IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157

    Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

    DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    125.
    发明申请
    DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220384341A1

    公开(公告)日：2022-12-01

    申请号：US17819004

    申请日：2022-08-11

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575

    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS
    128.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220149015A1

    公开(公告)日：2022-05-12

    申请号：US17649022

    申请日：2022-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

    IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/482

    Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

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