公开(公告)号：US09995775B2

公开(公告)日：2018-06-12

申请号：US13877317

申请日：2011-10-13

Applicant: Xiuzhen Dong ,  Xuyang Huo ,  Fusheng You ,  Xuetao Shi ,  Feng Fu ,  Ruigang Liu ,  Zhenyu Ji ,  Canhua Xu ,  Bin Yang ,  Min Yang ,  Jiaxue Qi ,  Wen Zhang ,  Nan Wang

Inventor： Xiuzhen Dong ,  Xuyang Huo ,  Fusheng You ,  Xuetao Shi ,  Feng Fu ,  Ruigang Liu ,  Zhenyu Ji ,  Canhua Xu ,  Bin Yang ,  Min Yang ,  Jiaxue Qi ,  Wen Zhang ,  Nan Wang

IPC: G01R27/02 ,  A61B5/053 ,  A61B5/00 ,  G01R27/14

CPC classification number: G01R27/02 ,  A61B5/053 ,  A61B5/0536 ,  A61B5/7225 ,  G01R27/14

Abstract: A device for detecting electrical impedance by utilizing a theory of excitation and response signals and method thereof, wherein the excitation signal is a square wave excitation current signal (1), the response signal on a target is transformed to a square wave signal with appropriate amplitudes by buffering, amplifying, RC filtering and differential amplifying, then is transformed to a digital signal at a proper time by an analog-to-digital converter. The response signal is sampled once when at high level and once when at low level for every circle by the ADC, and a sample V1 and a sample V2 are obtained respectively, difference of the samples is taken as a detecting result for one circle. An average value of the detecting result from a plurality of circles is taken as a final result. Information of electrical impedance is illustrated by the final result because the excitation current signal is constant.

公开(公告)号：US08981047B2

公开(公告)日：2015-03-17

申请号：US12739342

申请日：2008-10-23

Applicant: Richard D. Dimarchi ,  Bin Yang

Inventor： Richard D. Dimarchi ,  Bin Yang

IPC: A61K38/26 ,  C07K14/605 ,  C07K14/00 ,  A61K38/00

CPC classification number: C07K14/605 ,  A61K38/00

Abstract: Glucagon antagonists are provided which comprise amino acid substitutions and/or chemical modifications to glucagon sequence. In one embodiment, the glucagon antagonists comprise a native glucagon peptide that has been modified by the deletion of the first two to five amino acid residues from the N-terminus and (i) an amino acid substitution at position 9 (according to the numbering of native glucagon) or (ii) substitution of the Phe at position 6 (according to the numbering of native glucagon) with phenyl lactic acid (PLA). In another embodiment, the glucagon antagonists comprise the structure A-B-C as described herein, wherein A is PLA, an oxy derivative thereof, or a peptide of 2-6 amino acids in which two consecutive amino acids of the peptide are linked via an ester or ether bond.

Abstract translation: 提供了包含对胰高血糖素序列的氨基酸取代和/或化学修饰的胰高血糖素拮抗剂。 在一个实施方案中，胰高血糖素拮抗剂包含通过从N-末端缺失前两个至五个氨基酸残基而修饰的天然胰高血糖素肽，以及（i）在第9位的氨基酸取代（根据 天然胰高血糖素）或（ii）用苯基乳酸（PLA）取代第6位的Phe（根据天然胰高血糖素的编号）。 在另一个实施方案中，胰高血糖素拮抗剂包含如本文所述的结构ABC，其中A是PLA，其氧衍生物或2-6个氨基酸的肽，其中肽的两个连续氨基酸经由酯或醚连接 键。

公开(公告)号：US08889087B2

公开(公告)日：2014-11-18

申请号：US13948967

申请日：2013-07-23

Applicant: Anna Lee Y. Tonkovich ,  Robert D. Litt ,  Timothy M. Werner ,  Bin Yang

Inventor： Anna Lee Y. Tonkovich ,  Robert D. Litt ,  Timothy M. Werner ,  Bin Yang

IPC: B01J8/00 ,  B01J19/18 ,  B01J19/00 ,  C10G2/00 ,  C07C29/152

CPC classification number: B01J19/0093 ,  B01J19/1831 ,  B01J2219/00783 ,  B01J2219/00835 ,  B01J2219/00873 ,  B01J2219/00984 ,  C07C29/152 ,  C10G2/341 ,  C07C31/04

Abstract: An integrated microchannel reactor and heat exchanger comprising: (a) a waveform sandwiched between opposing shim sheets and mounted to the shim sheets to form a series of microchannels, where each microchannel includes a pair of substantially straight side walls, and a top wall formed by at least one of the opposing shim sheets, and (b) a first set of microchannels in thermal communication with the waveform, where the waveform has an aspect ratio greater than two.

Abstract translation: 一种集成微通道反应器和热交换器，包括：（a）夹在相对的垫片之间的波形并安装到垫片以形成一系列微通道，其中每个微通道包括一对基本上直的侧壁，以及由 至少一个相对的垫片，和（b）与波形热连通的第一组微通道，其中波形的纵横比大于2。

公开(公告)号：US08741753B2

公开(公告)日：2014-06-03

申请号：US13611736

申请日：2012-09-12

Applicant: Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

Inventor： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

IPC: H01L21/20 ,  H01L21/3205 ,  H01L21/00

CPC classification number: H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

Abstract: A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

Abstract translation: 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

公开(公告)号：US08685365B2

公开(公告)日：2014-04-01

申请号：US13747440

申请日：2013-01-22

Applicant: James A. Mathias ,  G. Bradley Chadwell ,  Annalee Y. Tonkovich ,  Steven T. Perry ,  Matthew B. Schmidt ,  Sean P. Fitzgerald ,  David J. Hesse ,  Thomas D. Yuschak ,  Bin Yang

Inventor： James A. Mathias ,  G. Bradley Chadwell ,  Dongming Qiu ,  Annalee Y. Tonkovich ,  Steven T. Perry ,  Matthew B. Schmidt ,  Sean P. Fitzgerald ,  David J. Hesse ,  Thomas D. Yuschak ,  Bin Yang

IPC: C01B3/24 ,  B01J19/00 ,  B01J8/00

CPC classification number: F16L41/02 ,  B01J19/0093 ,  B01J35/04 ,  B01J2219/00869 ,  B01J2219/00891 ,  C01B3/384 ,  C01B2203/0233 ,  C01B2203/0811 ,  C01B2203/0822 ,  F28D7/0066 ,  F28D9/0093 ,  F28F3/12 ,  F28F7/02 ,  F28F2260/02 ,  Y02P20/128 ,  Y02P20/52 ,  Y10T137/0318 ,  Y10T137/6579 ,  Y10T137/87153 ,  Y10T137/87249

Abstract: Provided is a process and device for exchanging heat energy between three or more streams in a microchannel heat exchanger which can be integrated with a microchannel reactor to form an integrated microchannel processing unit. The combining of a plurality of integrated microchannel devices to provide the benefits of large-scale operation is enabled. In particular, the microchannel heat exchanger enables flexible heat transfer between multiple streams and total heat transfer rates of about 1 Watt or more per core unit volume expressed as W/cc.

Abstract translation: 提供了一种用于在微通道热交换器中的三个或更多个流之间交换热能的过程和装置，其可以与微通道反应器集成以形成集成的微通道处理单元。 实现了多个集成微通道装置的组合以提供大规模操作的优点。 特别地，微通道热交换器使得能够在多个流之间实现柔性热传递，并且以W / cc表示的每单位体积的约1瓦或更高的总传热速率。

公开(公告)号：US08652963B2

公开(公告)日：2014-02-18

申请号：US13237732

申请日：2011-09-20

Applicant: Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

Inventor： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

Abstract translation: 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

公开(公告)号：US20140003649A1

公开(公告)日：2014-01-02

申请号：US13997258

申请日：2011-12-23

Applicant: Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

Inventor： Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

IPC: G06T1/00

CPC classification number: G06T1/0021 ,  G06K9/348 ,  G06K2209/01 ,  G06T2201/0051 ,  G06T2201/0062 ,  G06T2201/0083

Abstract: The application provides a method for partitioning a watermark image with western language characters, comprising: partitioning a western language characters image along rows and columns to form a plurality of character image blocks; identifying valid character image blocks from the formed character image blocks; counting sizes of the valid character image blocks to determine if the image corresponds to a document with a large font size or a document with a small font size; dividing words in the image into a plurality of groups, wherein each divided group in the document with large font size has different numbers of words from that with small font size; and dividing equally the divided word groups into multiple portions corresponding to watermark image blocks. The application further provides a device for partitioning a watermark image with western language characters. The operability of watermark embedding process can be ensured through the above technical solution.

Abstract translation: 该应用程序提供了一种用于用西方语言字符分割水印图像的方法，包括：沿着行和列划分西方语言字符图像以形成多个字符图像块; 从形成的字符图像块中识别有效的字符图像块; 计算有效字符图像块的大小，以确定图像是否对应于具有较大字体大小的文档或具有小字体大小的文档; 将图像中的单词划分成多个组，其中具有大字体大小的文档中的每个划分组具有与具有小字体尺寸的单词不同的字数; 并将划分的字组分成相当于水印图像块的多个部分。 该应用还提供了一种用于用西语字符分割水印图像的设备。 通过上述技术方案可以确保水印嵌入过程的可操作性。

公开(公告)号：US08518758B2

公开(公告)日：2013-08-27

申请号：US12726889

申请日：2010-03-18

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L27/12

CPC classification number: H01L29/78618 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

Abstract translation: 在诸如极薄的SOI（ETSOI）衬底的SOI衬底上形成半导体，具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层（例如嵌入硅锗（eSiGe））的半导体器件。 实施例包括形成SOI衬底，在SOI衬底上外延形成含硅层，并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后，去除栅电极和下面的含硅层，并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失，从而增加延伸厚度并降低延伸电阻。

公开(公告)号：US08456011B2

公开(公告)日：2013-06-04

申请号：US13006664

申请日：2011-01-14

Applicant: Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

Inventor： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

IPC: H01L23/532

CPC classification number: H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

公开(公告)号：US08413511B2

公开(公告)日：2013-04-09

申请号：US13015987

申请日：2011-01-28

Applicant: Zhou Ge ,  Bin Yang ,  Zheng-Kui Meng ,  Yi-Lin Yan ,  Rui Zhang

Inventor： Zhou Ge ,  Bin Yang ,  Zheng-Kui Meng ,  Yi-Lin Yan ,  Rui Zhang

IPC: G01P15/125

CPC classification number: G01P15/125 ,  G01P15/18 ,  G01P2015/082 ,  G01P2015/0848 ,  G01P2015/0854

Abstract: A accelerometer includes a substrate define a stationary electrode thereon, a first moveable mass defining a conductive-layer thereon facing the stationary electrode, a plurality of first elastic elements coupled with a peripheral side of the first moveable mass, a first fixed element surrounding the first moveable mass and fixedly attached to the substrate, a plurality of first fixed electrodes extending outwardly from the first fixed element, a second moveable mass surrounding the first fixed electrodes, a plurality of first moveable electrodes extending inwardly from the second moveable mass toward the first fixed element and parallel to the first fixed electrodes, respectively, a plurality of second elastic elements coupled with a peripheral side of the second moveable mass, and a second fixed element surrounding the second moveable mass and fixedly attached to the substrate.

Abstract translation: 加速度计包括在其上限定固定电极的基板，限定其面向固定电极的导电层的第一可移动质量块，与第一可移动质量块的周边连接的多个第一弹性元件，围绕第一 可移动的质量并且固定地附接到基板，从第一固定元件向外延伸的多个第一固定电极，围绕第一固定电极的第二可移动质量;从第二可移动质量向内朝向第一固定 并且与第一固定电极平行的多个第二弹性元件分别与第二可移动质量体的周边连接，第二固定元件围绕第二可移动质量块并且固定地附着在基底上。