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    SEMICONDUCTOR DEVICE
    122.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220149044A1

    公开(公告)日：2022-05-12

    申请号：US17579640

    申请日：2022-01-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H01L27/105 ,  H01L27/06 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108

    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

    MEMORY DEVICE AND ELECTRONIC DEVICE
    123.
    发明申请
    MEMORY DEVICE AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20210183860A1

    公开(公告)日：2021-06-17

    申请号：US17047143

    申请日：2019-04-11

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Takanori MATSUZAKI

    IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

    Abstract: A novel semiconductor device is provided. A semiconductor device includes a plurality of cell arrays and a plurality of peripheral circuits. The cell array includes a plurality of memory cells. The peripheral circuit includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit. The first driver circuit and the second driver circuit each have a function of supplying a selection signal to the cell array. The first amplifier circuit and the second amplifier circuit each have a function of amplifying a potential input from the cell array. The third amplifier circuit and the fourth amplifier circuit each have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit. The first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit have a region overlapping with the cell array. A transistor included in the memory cell includes a metal oxide in a channel formation region.

    MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    124.
    发明申请
    MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210167067A1

    公开(公告)日：2021-06-03

    申请号：US17061920

    申请日：2020-10-02

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

    IPC: H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/13 ,  H01L27/115 ,  H01L29/786

    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

    SEMICONDUCTOR DEVICE
    125.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210091083A1

    公开(公告)日：2021-03-25

    申请号：US16613478

    申请日：2018-05-07

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kiyoshi KATO

    IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

    Abstract: A semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first memory cell and a second memory cell. The first memory cell includes a first transistor. The second memory cell includes a second transistor. The threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. The first transistor includes a first metal oxide. The second transistor includes a second metal oxide. Each of the first metal oxide and the second metal oxide includes a channel formation region. Each of the first metal oxide and the second metal oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. The atomic ratio of the element M to In in the second metal oxide is greater than that in the first metal oxide.

    STORAGE DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
    126.
    发明申请
    STORAGE DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20210081023A1

    公开(公告)日：2021-03-18

    申请号：US17104460

    申请日：2020-11-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shuhei MAEDA ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO

    IPC: G06F1/3234 ,  G11C16/30 ,  G11C14/00 ,  G11C5/14

    Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

    Semiconductor Device
    128.
    发明申请
    Semiconductor Device 审中-公开

    公开(公告)号：US20200279589A1

    公开(公告)日：2020-09-03

    申请号：US16643755

    申请日：2018-09-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

    IPC: G11C7/06 ,  G11C14/00

    Abstract: To provide a novel semiconductor device.The semiconductor device includes cell arrays and peripheral circuits; the cell arrays include memory cells; the peripheral circuits includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit; the first driver circuit and the second driver circuit have a function of supplying a selection signal to the cell array; the first amplifier circuit and the second amplifier circuit have a function of amplifying a potential input from the cell array; the third amplifier circuit and the fourth amplifier circuit have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit; the first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit include a region overlapping with the cell array; and the memory cells include a metal oxide in a channel formation region.

    STORAGE DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
    129.
    发明申请
    STORAGE DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20190377401A1

    公开(公告)日：2019-12-12

    申请号：US16476642

    申请日：2018-01-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shuhei MAEDA ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO

    IPC: G06F1/3234 ,  G11C5/14 ,  G11C16/30 ,  G11C14/00

    Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

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