公开(公告)号：US20240332262A1

公开(公告)日：2024-10-03

申请号：US18740603

申请日：2024-06-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L25/065 ,  G11C5/06 ,  H01L23/00 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L25/0657 ,  G11C5/063 ,  H01L29/78693 ,  H10B12/315 ,  H10B12/50 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

公开(公告)号：US20240321205A1

公开(公告)日：2024-09-26

申请号：US18569779

申请日：2022-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Susumu KAWASHIMA ,  Yutaka OKAZAKI

IPC: G09G3/3233 ,  H01L27/088 ,  H01L27/12

CPC classification number: G09G3/3233 ,  H01L27/088 ,  H01L27/1225 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2330/021

Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

公开(公告)号：US20240284674A1

公开(公告)日：2024-08-22

申请号：US18586866

申请日：2024-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H10B43/27 ,  H01L29/24 ,  H01L29/51 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L29/24 ,  H01L29/513

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US20210249703A1

公开(公告)日：2021-08-12

申请号：US16973666

申请日：2019-07-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Ryota TAJIMA ,  Shunpei YAMAZAKI

IPC: H01M10/44 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H02J7/00 ,  H01M10/48

Abstract: A semiconductor device capable of charging that is less likely to cause deterioration of a power storage device is provided.
The amount of a charging current is adjusted in accordance with the ambient temperature. Charging under low-temperature environments is performed with a reduced charging current. When the ambient temperature is too low or too high, the charging is stopped. Measurement of the ambient temperature is performed with a memory element using an oxide semiconductor. The use of a memory element using an oxide semiconductor enables measurement of the ambient temperature and retention of the temperature information to be performed at the same time.

公开(公告)号：US20210183860A1

公开(公告)日：2021-06-17

申请号：US17047143

申请日：2019-04-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Takanori MATSUZAKI

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A novel semiconductor device is provided. A semiconductor device includes a plurality of cell arrays and a plurality of peripheral circuits. The cell array includes a plurality of memory cells. The peripheral circuit includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit. The first driver circuit and the second driver circuit each have a function of supplying a selection signal to the cell array. The first amplifier circuit and the second amplifier circuit each have a function of amplifying a potential input from the cell array. The third amplifier circuit and the fourth amplifier circuit each have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit. The first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit have a region overlapping with the cell array. A transistor included in the memory cell includes a metal oxide in a channel formation region.

公开(公告)号：US20200373302A1

公开(公告)日：2020-11-26

申请号：US16767645

申请日：2018-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Tomoaki ATSUMI ,  Takahiko ISHIZU

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

Abstract: A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.

公开(公告)号：US20200279589A1

公开(公告)日：2020-09-03

申请号：US16643755

申请日：2018-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G11C7/06 ,  G11C14/00

Abstract: To provide a novel semiconductor device.The semiconductor device includes cell arrays and peripheral circuits; the cell arrays include memory cells; the peripheral circuits includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit; the first driver circuit and the second driver circuit have a function of supplying a selection signal to the cell array; the first amplifier circuit and the second amplifier circuit have a function of amplifying a potential input from the cell array; the third amplifier circuit and the fourth amplifier circuit have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit; the first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit include a region overlapping with the cell array; and the memory cells include a metal oxide in a channel formation region.

公开(公告)号：US20190222209A1

公开(公告)日：2019-07-18

申请号：US16362777

申请日：2019-03-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI

IPC: H03K5/24 ,  H01L49/02 ,  H01L27/146 ,  H01L27/108 ,  H01L23/498 ,  G11C5/14 ,  H01L21/78 ,  H01L27/00

CPC classification number: H03K5/2481 ,  G11C5/144 ,  G11C5/145 ,  H01L21/78 ,  H01L23/49844 ,  H01L27/00 ,  H01L27/10805 ,  H01L27/14687 ,  H01L28/00

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

公开(公告)号：US20180005668A1

公开(公告)日：2018-01-04

申请号：US15626595

申请日：2017-06-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Kiyoshi KATO ,  Takanori MATSUZAKI

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C5/063 ,  G11C11/403 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097 ,  H01L21/8258 ,  H01L27/0222 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24 ,  H01L29/7869

Abstract: To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.

公开(公告)号：US20170230041A1

公开(公告)日：2017-08-10

申请号：US15427815

申请日：2017-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI

IPC: H03K5/24 ,  H01L21/78 ,  H01L23/498

CPC classification number: H03K5/2481 ,  G11C5/144 ,  G11C5/145 ,  H01L21/78 ,  H01L23/49844 ,  H01L27/00 ,  H01L27/10805 ,  H01L27/14687 ,  H01L28/00

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.