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    High perfomance DMA controller for video processors
    121.
    发明授权
    High perfomance DMA controller for video processors 有权
    用于视频处理器的高性能DMA控制器

    公开(公告)号：US09372817B2

    公开(公告)日：2016-06-21

    申请号：US14330553

    申请日：2014-07-14

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan

    IPC: H04N19/433 ,  G06F13/28

    CPC classification number: G06F13/28

    Abstract: This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and reduces CPU intervention using virtual alignment, sub-tile optimization, transaction breakdown strategy, 4D indexing, a dedicated interface with the host and frame padding. The VDMA has separate buffers for non-determinative synchronous data transfers and determinative asynchronous data transfers.

    Abstract translation: 用于VDMA的本发明将实现每秒30帧的超高分辨率（4K）编码/解码。 本发明使互连/ DDR利用率最大化，并使用虚拟对准，子块优化，事务分解策略，4D索引，与主机和帧填充的专用接口来减少CPU干预。 VDMA具有用于非确定性同步数据传输和确定性异步数据传输的单独缓冲器。

    METHOD AND APPARATUS OF HEVC DE-BLOCKING FILTER
    122.
    发明申请
    METHOD AND APPARATUS OF HEVC DE-BLOCKING FILTER 有权
    HEVC阻塞过滤器的方法和装置

    公开(公告)号：US20140341271A1

    公开(公告)日：2014-11-20

    申请号：US14282211

    申请日：2014-05-20

    Applicant: Texas Instruments Incorporated

    Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

    IPC: H04N19/117 ,  H04N19/176 ,  H04N19/50 ,  H04N19/13 ,  H04N19/107 ,  H04N19/119 ,  H04N19/124 ,  H04N19/60

    CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/186 ,  H04N19/82 ,  H04N19/86

    Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

    Abstract translation: 提供了一种解封处理视频的过滤方法。 经处理的视频包括多个块，并且每个块包括多个子块。 多个块中的当前块包括垂直边缘和水平边缘。 经处理的视频还包括一组对应于当前块的控制参数和重构像素。 在当前块的垂直边缘和水平边缘估计边界强度指数。 加载控制参数集合，对应于当前块的重构像素和对应于一组相邻子块的部分滤波像素。 基于边界强度指数和控制参数集合对当前块的垂直边缘和水平边缘进行滤波，使得在对当前块的至少一个水平边缘进行滤波之前对当前块的垂直边缘进行滤波。

    Suppression of clipping artifacts from color conversion
    123.
    发明授权
    Suppression of clipping artifacts from color conversion 有权

    公开(公告)号：US12131504B2

    公开(公告)日：2024-10-29

    申请号：US17538268

    申请日：2021-11-30

    Applicant: Texas Instruments Incorporated

    Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

    IPC: G06K9/00 ,  G06T1/20 ,  G06T7/90

    CPC classification number: G06T7/90 ,  G06T1/20 ,  G06T2207/10024 ,  G06T2207/20208

    Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.

    Scheduling of External Block Based Data Processing Tasks on a Hardware Thread Scheduler
    124.
    发明公开
    Scheduling of External Block Based Data Processing Tasks on a Hardware Thread Scheduler 审中-公开

    公开(公告)号：US20240345870A1

    公开(公告)日：2024-10-17

    申请号：US18748423

    申请日：2024-06-20

    Applicant: Texas Instruments Incorporated

    Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

    IPC: G06F9/48 ,  G06F9/50

    CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

    Abstract: Systems and method are provided for flexibly configuring task schedulers and respectively associated data processing nodes to execute threads of tasks using a hardware thread scheduler (HTS). The data processing nodes may be hardware accelerators, channels of a direct memory access circuit and external nodes such as a processor executing software instructions. Each hardware accelerator is coupled to a respective hardware task scheduler, each channel is coupled to a respective channel task scheduler, and each external node is coupled to a proxy task scheduler. The task schedulers communicate via pending and decrement signals with a hardware scheduler crossbar. With this arrangement, the HTS couples a first subset of task schedulers in a first data processing order with the associated data processing nodes performing the tasks, and couples a second subset of task schedulers in a second data processing order with the associated data processing nodes performing the tasks.

    VARIABLE-SIZED PIXEL GROUPINGS AND BUFFER MANAGEMENT FOR PROCESSING DISTORTED IMAGE DATA
    125.
    发明公开
    VARIABLE-SIZED PIXEL GROUPINGS AND BUFFER MANAGEMENT FOR PROCESSING DISTORTED IMAGE DATA 审中-公开

    公开(公告)号：US20240221133A1

    公开(公告)日：2024-07-04

    申请号：US18148244

    申请日：2022-12-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Niraj Nandan ,  Rajasekhar Allu ,  Mihir Narenda Mody ,  Ankur Ankur ,  Pandy Kalimuthu

    IPC: G06T5/00 ,  G06T1/60

    CPC classification number: G06T5/006 ,  G06T1/60

    Abstract: Various embodiments disclosed herein relate to distorted pixel correction, and more specifically to producing an output image using variable-sized groupings of lines of pixels of an input image. An example embodiment includes a method of using variable-sized pixel groupings when processing distorted image data. The method comprises identifying a context of an image captured by an imaging system, wherein the image comprises lines of pixels that form a distorted representation of a scene, identifying, based on the context of the image, a mapping of variable-sized groupings of the lines to memory ranges in a buffer, wherein an image processing subsystem produces block rows of an output image based on the mapping, and wherein a size of each of the variable-sized groupings varies based on how many of the lines the image processing subsystem uses to produce each of the block rows, and supplying the mapping to the image processing subsystem.

    Method and apparatus of HEVC de-blocking filter
    126.
    发明授权
    Method and apparatus of HEVC de-blocking filter 有权

    公开(公告)号：US12010330B2

    公开(公告)日：2024-06-11

    申请号：US18123432

    申请日：2023-03-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

    IPC: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

    CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

    Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

    OPTIMIZED EDGE ORDER FOR DE-BLOCKING FILTER
    128.
    发明公开
    OPTIMIZED EDGE ORDER FOR DE-BLOCKING FILTER 审中-公开

    公开(公告)号：US20230353789A1

    公开(公告)日：2023-11-02

    申请号：US18219788

    申请日：2023-07-10

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

    IPC: H04N19/80 ,  H04N19/86 ,  H04N19/423

    CPC classification number: H04N19/80 ,  H04N19/423 ,  H04N19/86

    Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

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