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公开(公告)号：US20240045589A1
公开(公告)日：2024-02-08
申请号：US18488581
申请日：2023-10-17
Inventor： Nitin CHAWLA , Giuseppe DESOLI , Anuj GROVER , Thomas BOESCH , Surinder Pal SINGH , Manuj AYODHYAWASI
CPC classification number: G06F3/0604 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06N3/08
Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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122.发明授权公开(公告)号：US11885849B2
公开(公告)日：2024-01-30
申请号：US17483014
申请日：2021-09-23
Applicant: Cartesiam
Inventor： He Huang , Francois De Grimaudet De Rochebouet
IPC: G01R31/34 , G06N20/00 , G01R19/165
CPC classification number: G01R31/343 , G01R19/165 , G06N20/00
Abstract: A method can be used for supervising the operation of a machine powered with electric current. The method includes operating the machine in a normal operation mode, repeatedly performing a learning phase for learning the normal operation machine of the machine to create a knowledge base, autonomously switching from the learning phase into a supervision phase when the knowledge base is considered to have been created, and repeatedly performing the supervision phase.
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公开(公告)号：US20240005956A1
公开(公告)日：2024-01-04
申请号：US18448737
申请日：2023-08-11
Applicant: STMicroelectronics International N.V.
Inventor： Paolo Pulici , Michele Bartolini , Enrico Sentieri , Enrico Mammei , Matteo Tonelli , Dennis Hogg
IPC: G11B5/60
CPC classification number: G11B5/607 , G11B5/6017
Abstract: A system for determining a fly height includes a first head of a disk drive, a second head of the disk drive, a capacitive sensor circuit coupled to the first head and the second head, and a logic device coupled to the capacitive sensor circuit. The capacitive sensor circuit is configured to measure a first capacitance between the first head and the first disk, remove noise from the first capacitance using a second capacitance between the second head and the second disk, and based thereon determine a corrected first capacitance. The logic device is configured to determine the fly height between the first head and the first disk using the corrected first capacitance.
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公开(公告)号：US11863066B2
公开(公告)日：2024-01-02
申请号：US18168936
申请日：2023-02-14
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US11860993B2
公开(公告)日：2024-01-02
申请号：US17396137
申请日：2021-08-06
Applicant: STMicroelectronics International N.V.
Inventor： Dhulipalla Phaneendra Kumar
Abstract: A method of operating an electronic device includes generating scramble control codes. The scramble codes are generated by generating a random number, shifting the random number to produce a shifted random number, generating control signals by selecting different subsets of the shifted random number, and generating scramble control words by selecting different subsets of the random number based upon the control signals. The method further includes receiving a password comprised of sub-words and scrambling those sub-words according to the scramble control codes, retrieving a verification word comprised of sub-words and scrambling those sub-words according to the scramble control codes, and comparing the scrambled sub-words of the password to the scrambled sub-words of the verification word to thereby authenticate an external device that provided the password.
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Patent Agency Ranking
公开(公告)号：US20230409341A1
公开(公告)日：2023-12-21
申请号：US18312237
申请日：2023-05-04
Inventor： Asif Rashid Zargar , Roberto Colombo
IPC: G06F9/4401 , G06F21/64
CPC classification number: G06F9/4405 , G06F21/64
Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.
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127.发明公开公开(公告)号：US20230396155A1
公开(公告)日：2023-12-07
申请号：US17834174
申请日：2022-06-07
Applicant: STMicroelectronics International N.V.
Inventor： Ranajay MALLIK , Akshat JAIN
CPC classification number: H02M1/4216 , H02M1/4225 , H02M1/4233 , H02M1/12
Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.
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公开(公告)号：US11835991B2
公开(公告)日：2023-12-05
申请号：US17208935
申请日：2021-03-22
Applicant: STMicroelectronics International N.V.
IPC: G06F11/27 , G01R31/3177 , G06F1/08
CPC classification number: G06F11/27 , G01R31/3177 , G06F1/08
Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.
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公开(公告)号：US11829730B2
公开(公告)日：2023-11-28
申请号：US17940654
申请日：2022-09-08
Inventor： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
CPC classification number: G06F7/57 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06N3/063
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US11798603B2
公开(公告)日：2023-10-24
申请号：US18175375
申请日：2023-02-27
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
CPC classification number: G11C7/12 , G11C7/065 , G11C7/222 , G11C11/4091 , G11C11/4094
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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