公开(公告)号：US08704329B2

公开(公告)日：2014-04-22

申请号：US13503684

申请日：2010-12-29

Applicant: Ming Qiao ,  Bo Luo ,  Xi Hu ,  Jun Ye ,  Bo Zhang ,  Zhaoji Li

Inventor： Ming Qiao ,  Bo Luo ,  Xi Hu ,  Jun Ye ,  Bo Zhang ,  Zhaoji Li

IPC: H01L29/00

CPC classification number: H01L27/1203 ,  H01L29/7317 ,  H01L29/7394

Abstract: SOI devices for plasma display panel driver chip, include a substrate, a buried oxide layer and an n-type SOI layer in a bottom-up order, where the SOI layer is integrated with an HV-NMOS device, an HV-PMOS device, a Field-PMOS device, an LIGBT device, a CMOS device, an NPN device, a PNP device and an HV-PNP device; the SOI layer includes an n+ doped region within the SOI layer at an interface between the n-type SOI layer and the buried oxide layer; and the n+ doped region has a higher doping concentration than the n-type SOI layer.

Abstract translation: 用于等离子体显示面板驱动器芯片的SOI器件包括自底向上的衬底，掩埋氧化物层和n型SOI层，其中SOI层与HV-NMOS器件，HV-PMOS器件， 场PMOS器件，LIGBT器件，CMOS器件，NPN器件，PNP器件和HV-PNP器件; SOI层在n层SOI层和掩埋氧化物层之间的界面处包括在SOI层内的n +掺杂区域; 并且n +掺杂区域具有比n型SOI层更高的掺杂浓度。

公开(公告)号：US08648887B2

公开(公告)日：2014-02-11

申请号：US13245215

申请日：2011-09-26

Applicant: Shulin Tian ,  Peng Ye ,  Lianping Guo ,  Jun Jiang ,  Duyu Qiu ,  Qinchuan Zhang ,  Hao Zeng ,  Chuanyun Xiang ,  Kuojun Yang

Inventor： Shulin Tian ,  Peng Ye ,  Lianping Guo ,  Jun Jiang ,  Duyu Qiu ,  Qinchuan Zhang ,  Hao Zeng ,  Chuanyun Xiang ,  Kuojun Yang

IPC: G09G5/10

CPC classification number: G01R13/0227

Abstract: A method for adjusting the waveform brightness for a waveform formatted to be displayed on a digital three-dimensional (3D) oscilloscope having M brightness gradation levels to display the waveform on a digital 3D oscilloscope having L brightness gradation levels is includes, creating a ROM in an FPGA and storing a look-up table of screen display brightness value of LCD that is corresponding to the waveform occurrence N(T,A) at the current brightness gradation L. The ROM is divided into 2a sub ROMs, each sub ROM has the capacity of 2b×d bits. A value of round(pL·N(T,A) is assigned to waveform brightness value D(T,A) and is stored correspondingly into the subROML of 2b×d bits by ascending order of the b bits of binary data of waveform occurrence N(T,A). In this way, using the b bits of binary data of waveform occurrence N(T,A) as the binary address of the subROML, corresponding waveform brightness value D(T,A) at the current brightness gradation L can be obtained through look-up table in the subROML.

Abstract translation: 一种用于调整格式化以显示在具有M个亮度灰度级的数字三维（3D）示波器上的波形的波形亮度的方法，用于在具有L个亮度灰度级的数字3D示波器上显示该波形，该方法包括： FPGA，并存储与当前亮度等级L对应的波形发生N（T，A）的LCD的屏幕显示亮度值的查找表.ROM被分成2a个子ROM，每个子ROM具有 容量为2b×d位。 将圆值（pL·N（T，A））分配给波形亮度值D（T，A），并通过波形发生的二进制数据的b位的升序相应地存储在2b×d位的subROML中 N（T，A）以这种方式使用波形发生N（T，A）的二进制数据的b位作为subROML的二进制地址，相应的波形亮度值D（T，A） L可以通过subromL中的查找表获得。

公开(公告)号：US08598658B2

公开(公告)日：2013-12-03

申请号：US13577360

申请日：2011-04-28

Applicant: Jian Fang ,  Lvyun Chen ,  Wenchang Li ,  Chao Guan ,  Qiongle Wu ,  Wenbin Bo ,  Zehua Wang

Inventor： Jian Fang ,  Lvyun Chen ,  Wenchang Li ,  Chao Guan ,  Qiongle Wu ,  Wenbin Bo ,  Zehua Wang

IPC: H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41758

Abstract: A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.

Abstract translation: 高压横向双扩散金属氧化物半导体场效应晶体管（LDMOS）包括衬底; 衬底上的外延层; 外延层上的漂移区; 以及两端的漏极区域和源极区域。 至少一对n型和p型半导体区域交替地布置在衬底和外延层的界面上方并且牢固地附着到漂移区域的下表面上; n型和p型半导体区域彼此牢固地封闭并且被布置成形成横向PN结; 并且p型半导体区域和漂移区域形成垂直PN结。 n型和p型半导体区也被称为“体内的还原表面场（RESURF）”，具有RESURF层的LDMOS器件有效地解决了提高反向耐压和减小正向电压之间的冲突， 当前LDMOS器件的电阻。

公开(公告)号：US20130214355A1

公开(公告)日：2013-08-22

申请号：US13577360

申请日：2011-04-28

Applicant: Jian Fang ,  Lvyun Chen ,  Wenchang Li ,  Chao Guan ,  Qiongle Wu ,  Wenbin Bo ,  Zehua Wang

Inventor： Jian Fang ,  Lvyun Chen ,  Wenchang Li ,  Chao Guan ,  Qiongle Wu ,  Wenbin Bo ,  Zehua Wang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41758

Abstract: A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.

Abstract translation: 高压横向双扩散金属氧化物半导体场效应晶体管（LDMOS）包括衬底; 衬底上的外延层; 外延层上的漂移区; 以及两端的漏极区域和源极区域。 至少一对n型和p型半导体区域交替地布置在衬底和外延层的界面上方并且牢固地附着到漂移区域的下表面上; n型和p型半导体区域彼此牢固地封闭并且被布置成形成横向PN结; 并且p型半导体区域和漂移区域形成垂直PN结。 n型和p型半导体区也被称为“体内的还原表面场（RESURF）”，具有RESURF层的LDMOS器件有效地解决了提高反向耐压和减小正向电压之间的冲突， 当前LDMOS器件的电阻。

公开(公告)号：US08404127B2

公开(公告)日：2013-03-26

申请号：US12831110

申请日：2010-07-06

Applicant: Yadong Jiang ,  Tao Wang ,  Deen Gu ,  Kai Yuan

Inventor： Yadong Jiang ,  Tao Wang ,  Deen Gu ,  Kai Yuan

IPC: H01B13/00

CPC classification number: G01J5/024 ,  G01J5/20 ,  H01L21/02565 ,  H01L21/0262

Abstract: A metal vanadium film is used as an extraction electrode contacting with a vanadium oxide or doped vanadium oxide film. The electrode material is adapted for a detector, sensor and optical switch based on a vanadium oxide or doped vanadium oxide film. The metal vanadium film is in favor of reducing the thermal conductivity of the support structure of the array unit. The preparation process of the vanadium film using the metal vanadium as the source material is more easily controlled than that of NiCr film using the NiCr alloy as the source material. The extraction electrode of the present invention easily obtains an excellent metal-semiconductor contact characteristic. The preparation process and patterning process of the metal vanadium film have an excellent technology compatibility with the IC and MEMS manufacturing processes.

Abstract translation: 使用金属钒膜作为与钒氧化物或掺杂氧化钒膜接触的提取电极。 电极材料适用于基于钒氧化物或掺杂氧化钒膜的检测器，传感器和光学开关。 金属钒膜有利于降低阵列单元的支撑结构的导热性。 使用金属钒作为源材料的钒膜的制备方法比使用NiCr合金作为源材料的NiCr膜更容易控制。 本发明的提取电极容易获得优异的金属 - 半导体接触特性。 金属钒膜的制备工艺和图案化工艺与IC和MEMS制造工艺具有很好的技术兼容性。

公开(公告)号：US20120168856A1

公开(公告)日：2012-07-05

申请号：US13033701

申请日：2011-02-24

Applicant: Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

Inventor： Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66734 ,  H01L29/7397

Abstract: The present invention relates to a semiconductor device. The device comprises a semiconductor substrate. A semiconductor drift region is on the semiconductor substrate. The semiconductor drift region comprises a semiconductor region of a first conduction type and a semiconductor region of a second conduction type. The semiconductor region of the first conduction type and the semiconductor region of the second conduction type form a superjunction structure. A high-K dielectric is on the semiconductor substrate. The high-K dielectric is adjacent to the semiconductor region of the second conduction type. An active region is on the semiconductor drift region. A trench gate structure is on the high-K dielectric, the trench gate structure being adjacent to the active region. The semiconductor region of the second conduction type is formed by shallow angle ion implantation, thus its width is narrow and its concentration is high.

Abstract translation: 本发明涉及一种半导体器件。 该器件包括半导体衬底。 半导体漂移区位于半导体衬底上。 半导体漂移区域包括第一导电类型的半导体区域和第二导电类型的半导体区域。 第一导电类型的半导体区域和第二导电类型的半导体区域形成超结构结构。 高K电介质在半导体衬底上。 高K电介质与第二导电类型的半导体区域相邻。 有源区位于半导体漂移区上。 沟槽栅极结构位于高K电介质上，沟槽栅极结构邻近有源区。 第二导电类型的半导体区域通过浅角离子注入形成，其宽度窄并且其浓度高。

公开(公告)号：US20110223771A1

公开(公告)日：2011-09-15

申请号：US12724165

申请日：2010-03-15

Applicant: Yadong Jiang ,  Zhiming Wu ,  Tao Wang ,  Weizhi Li ,  Xiaolin Han

Inventor： Yadong Jiang ,  Zhiming Wu ,  Tao Wang ,  Weizhi Li ,  Xiaolin Han

IPC: H01L21/306

CPC classification number: H01L21/67028 ,  B81C1/00571 ,  B81C2201/0133 ,  H01L21/32134 ,  H01L21/67086

Abstract: The present invention provides a method of wet etching a silicon slice including a silicon substrate and a metal film layer thereon comprising steps of: performing lithographic process to the silicon slice forming a masked silicon slice comprising the silicon substrate and a partially masked metal film thereon; immersing the masked silicon slice into an etchant; rotating the masked silicon slice in the etchant; injecting high-purity nitrogen gas into the etchant for agitating the etchant; removing the masked silicon slice out of the etchant, upon completion of etching; and rinsing the masked silicon slice with deionized water.

Abstract translation: 本发明提供了一种湿式蚀刻包括硅衬底和金属膜层的硅片的方法，包括以下步骤：对形成包含硅衬底和部分掩蔽的金属膜的掩模硅片的硅片进行光刻处理; 将掩蔽的硅片浸入蚀刻剂中; 在蚀刻剂中旋转掩模的硅片; 将高纯度氮气注入蚀刻剂以搅拌蚀刻剂; 蚀刻完成后将掩模的硅片从蚀刻剂上除去; 并用去离子水冲洗掩蔽的硅片。

公开(公告)号：US20110221351A1

公开(公告)日：2011-09-15

申请号：US12770725

申请日：2010-04-30

Applicant: Yadong Jiang ,  Junsheng Yu ,  Lu Li ,  Lei Zhang

Inventor： Yadong Jiang ,  Junsheng Yu ,  Lu Li ,  Lei Zhang

IPC: G09G3/12 ,  H01L21/66

CPC classification number: H01L27/3258 ,  H01L51/5237

Abstract: The present invention discloses an active matrix organic electroluminescence device comprising a thin-film transistor, an organic electroluminescence device, and an interlayer deposited between the thin-film transistor and the organic electroluminescence device, wherein the interlayer is made of cationic ultraviolet-curing adhesive comprising epoxy resin or modified epoxy resin, diluting agent, cationic photo initiator. The interlayer solves poor adhesiveness between the driving circuit and the organic electroluminescence device, and improves the moisture and oxygen proof ability. The preparation method is simple, effective, and able to lower the cost and difficulty, and greatly improve the yield rate.

Abstract translation: 本发明公开了一种有源矩阵有机电致发光器件，其包括薄膜晶体管，有机电致发光器件和沉积在薄膜晶体管和有机电致发光器件之间的中间层，其中中间层由阳离子紫外线固化粘合剂制成，其包含 环氧树脂或改性环氧树脂，稀释剂，阳离子光引发剂。 该夹层解决了驱动电路与有机电致发光元件之间的差的粘合性，提高了耐湿性和耐氧化性。 制备方法简单，有效，能降低成本和难度，大大提高产率。

公开(公告)号：US20110196961A1

公开(公告)日：2011-08-11

申请号：US12917999

申请日：2010-11-02

Applicant: Sheng WANG ,  Jing Ren ,  Du Xu ,  Shizhong Xu

Inventor： Sheng WANG ,  Jing Ren ,  Du Xu ,  Shizhong Xu

IPC: G06F15/173

CPC classification number: H04L63/1458

Abstract: The present invention relates to a method for detecting Network Anomaly in network architectures based on locator/identifier split, the detection flow is as follows: initialization processing, and in ITR: processing data packets, sending a Map-Request, determining whether to send an additional Map-Request, sending the data packet, processing the Map_Reply, processing EID-to-RLOC Cache entry expired; in ETR: processing data packet, processing Map-Request, determining whether the traffic of the ITR currently sending the Map-Request is abnormal, replying to the ITR of which the query traffic is abnormal, replying to ITR of which the query traffic is abnormal. With respect to the characteristic that the network architecture based on locator/identifier split needs to query the relationship between the locator and the identifier for packet delivery, the present invention detects Network Anomaly based on query traffic instead of network data packet traffic. Thus the present invention has the advantages of effectively reducing the investment on detection device, The overhead of exchanging monitoring information and the detection system maintenance cost; facilitating cross domain coordination; and efficiently handling the failures occurring during network operation in time; effectively improve the reliability of the network, being suitable for a large-scale network.

Abstract translation: 本发明涉及一种基于定位器/标识符分割的网络架构网络异常检测方法，检测流程如下：初始化处理，ITR处理数据包，发送地图请求，确定是否发送 附加映射请求，发送数据包，处理Map_Reply，处理EID到RLOC缓存条目过期; 在ETR中：处理数据包，处理Map-Request，确定当前发送Map-Request的ITR的流量是否异常，回复查询流量异常的ITR，回复查询流量异常的ITR 。 基于定位器/标识符分割的网络架构需要查询定位器与分组传送的标识符之间的关系，本发明基于查询流量而不是网络数据包流量来检测网络异常。 因此，本发明具有有效降低检测装置投资，交换监控信息和检测系统维护成本的开销; 促进跨域协调; 及时有效地处理网络运行过程中发生的故障; 有效提高网络的可靠性，适合大型网络。

公开(公告)号：US5216275A

公开(公告)日：1993-06-01

申请号：US761407

申请日：1991-09-17

Applicant: Xingbi Chen

Inventor： Xingbi Chen

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/73 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/73 ,  H01L29/7392 ,  H01L29/7802 ,  H01L29/861 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095

Abstract: A semiconductor power device wherein the reverse voltage across the p.sup.+ -regions(s) and the n.sup.+ -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n.sup.+ (or p.sup.+)-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V.sub.B of the CB-layer invented is Ron ocV.sub.B.sup.113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.

Abstract translation: 一种半导体功率器件，其中跨越p +区和n +区的反向电压由复合缓冲层维持，不久之后为CB层。 CB层包含两种具有相反导通类型的半导体区域。 从平行于层本身与n +（或p +） - 区域之间的界面的任何横截面观察，这两种区域可选地布置。 而在迄今使用的电压维持层中，在同一截面图中仅包含一种具有单一导电类型的半导体。 本发明还提供了设计指南。 单位面积Ron中的导通电阻与发明的CB层的击穿电压VB之间的关系为Ron ocVB113，这代表了传统电压维持层的突破，而功率器件的其他性能几乎保持不变。