公开(公告)号：US06883067B2

公开(公告)日：2005-04-19

申请号：US10072814

申请日：2002-02-08

Applicant: Trefor Southwell ,  Peter Hedinger ,  Kristen Jacobs

Inventor： Trefor Southwell ,  Peter Hedinger ,  Kristen Jacobs

IPC: G06F9/45 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F8/4442

Abstract: A memory map evaluation tool is provided that organizes a program in a manner most compatible with use of a cache. The tool includes a method that involves executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.

Abstract translation: 提供了以与缓存的使用最相容的方式组织程序的存储器映射评估工具。 该工具包括一种方法，其涉及根据第一存储器映射执行程序的第一版本以生成程序计数器跟踪，将程序计数器跟踪转换为特定格式，然后使用存储器映射将程序计数器跟踪转换为物理地址 被评估，不同于第一个存储器映射。 然后，这些物理地址用于使用正在评估的内存映射的直接映射高速缓存的模型来评估可能的高速缓存未命中的数量。

公开(公告)号：US20050055489A1

公开(公告)日：2005-03-10

申请号：US10658595

申请日：2003-09-09

Applicant: Paul Elliott

Inventor： Paul Elliott

IPC: G06F5/06 ,  G06F5/10 ,  G06F13/36

CPC classification number: G06F5/10 ,  G06F5/065

Abstract: A bridge circuit includes two FIFO circuits each having an associated FIFO control circuit. In each FIFO control circuit, a write pointer register and a read pointer register for controlling the storage location for writing to and reading from the FIFO circuit are each controlled by control logic. The control logic is responsive to comparators which receive and compare the write pointer value and the retimed read pointer value to control the write pointer register, and receive and compare the read pointer value and the retimed write pointer value to control the read pointer register. The retiming circuits are configurable in response to a mode signal to provide different degrees of retiming. The maximum number of storage locations that can be full at any one time is a fixed limit.

Abstract translation: 桥接电路包括两个FIFO电路，每个具有相关的FIFO控制电路。 在每个FIFO控制电路中，用于控制用于写入和读取FIFO电路的存储位置的写指针寄存器和读指针寄存器均由控制逻辑控制。 控制逻辑响应于比较器，其接收并比较写指针值和重定时读指针值以控制写指针寄存器，并且接收并比较读指针值和重定时写指针值以控制读指针寄存器。 重新定时电路可以响应于模式信号而配置，以提供不同程度的重新定时。 任何时间可以充满的存储位置的最大数量是固定的限制。

公开(公告)号：US06859850B1

公开(公告)日：2005-02-22

申请号：US09240176

申请日：1999-01-29

Applicant: Andrew MacCormack

Inventor： Andrew MacCormack

IPC: H04N5/00 ,  G06F13/00

CPC classification number: H04N21/434

Abstract: A controller for controlling direct memory access. Such a controller is particularly applicable when applied to a transport interface in the receiver of a digital set-top-box for television systems. A storage means stores the base and top addresses of a circular buffer in a memory to which received data is to be forwarded and stored, and a write pointer for such buffer is also stored in the storage means. Addressing circuitry generates the address to which the receive data is to be written in dependence on the stored base and top addresses and the write pointer. Output circuitry writes the data into the circular buffer at the location identified by the generated address.

Abstract translation: 用于控制直接存储器访问的控制器。 当应用于用于电视系统的数字机顶盒的接收机中的传输接口时，这种控制器特别适用。 存储装置将循环缓冲器的基地址和顶部地址存储在要被转发和存储接收数据的存储器中，并且用于这种缓冲器的写指针也存储在存储装置中。 寻址电路根据存储的基地址和顶部地址以及写入指针生成要写入接收数据的地址。 输出电路将数据写入由生成的地址标识的位置的循环缓冲区。

公开(公告)号：US20050013183A1

公开(公告)日：2005-01-20

申请号：US10830717

申请日：2004-04-23

Applicant: Trefor Southwell

Inventor： Trefor Southwell

IPC: G06F9/38 ,  G06F12/14 ,  G11C7/00

CPC classification number: G06F12/145 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1441

Abstract: A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.

Abstract translation: 一种用于验证投机负载操作的方法和系统。 该系统识别可能在代码序列中执行的推测加载操作，并且在将推测负载的虚拟地址转换为物理地址之后，推测负载控制单元用于定义多个存储器区域，并且具有用于检查是否 物理地址位于所述定义的存储区域的至少一个内。 以这种方式，控制单元允许将大的物理页面大小映射到RAM设备，并且由控制单元滤除额外的地址空间，以便在未知区域中不执行推测负载。

公开(公告)号：US06844896B2

公开(公告)日：2005-01-18

申请号：US09932822

申请日：2001-08-17

Applicant: Robert Henderson ,  Stewart Gresty Smith ,  Jonathan Ephriam David Hurwitz

Inventor： Robert Henderson ,  Stewart Gresty Smith ,  Jonathan Ephriam David Hurwitz

IPC: H04N5/217 ,  H04N5/357 ,  H04N5/365 ,  H04N5/378

CPC classification number: H04N5/3658 ,  H04N5/3575 ,  H04N5/378

Abstract: Solid state image sensors, and methods of operation thereof, includes an array of photosensitive pixels arranged in rows and columns and in which pixel data signals are read out from the pixels via column circuits, which introduces column fixed pattern noise to the signals. The signals are selectively inverted at the inputs to the column circuits and the inversion is reversed following output from the column circuits. Each column circuit may include an analog-to-digital converter and a digital inverter for inverting digital output therefrom. The selective inversion may be applied to alternate rows or groups of rows of the pixel data, and may be applied differently to different frames of the pixel data. These techniques result in column fixed pattern noise being modulated in a manner which makes the noise less apparent to the eye, and which facilitates subsequent cancellation of the noise.

Abstract translation: 固态图像传感器及其操作方法包括以列和列排列的光敏像素的阵列，其中通过列电路从像素读出像素数据信号，该列电路将列固定图案噪声引入信号。 这些信号在列电路的输入端被选择性地反相，并且在从列电路输出之后反转反转。 每列电路可以包括模数转换器和用于反转数字输出的数字反相器。 选择性反转可以应用于像素数据的行的交替行或组，并且可以不同地应用于像素数据的不同帧。 这些技术导致列固定模式噪声以使噪声对眼睛不太明显的方式进行调制，并且有助于随后的噪声消除。

公开(公告)号：US20040122881A1

公开(公告)日：2004-06-24

申请号：US10632530

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.l.

Inventor： Philip Mattos ,  Marco Losi

IPC: G06F017/15

CPC classification number: G01S19/37 ,  G01S19/24 ,  G01S19/29 ,  G01S19/30 ,  H04B1/708 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，包括两个循环移位寄存器的存储装置循环接收信号的采样，以便与本地生成的GPS码版本相关。 在跟踪模式中，采样信号被直接提供给相关器。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US20040004977A1

公开(公告)日：2004-01-08

申请号：US10421317

申请日：2003-04-22

Applicant: STMicroelectronics Limited

Inventor： William Robbins ,  David Wilkins

IPC: H04J003/04

CPC classification number: H04N21/434

Abstract: There is disclosed a circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data, so as to retain only those parts of the digital data stream required by the receiver. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver. A first control circuit extracts a packet identifier from an input data packet in the digital data stream, and generates a signal in dependence on whether the input data packet is of the first or second type. Sets of information associated with the first types of data packets and required by the receiver are stored in a memory under the control of a second control circuit. A third control circuit, responsive to receipt of the first type of input data packet, determines whether at least part of the input data packet matches the stored sets of information, and sets a match signal responsive thereto.

Abstract translation: 公开了一种用于在接收机中解复用包括至少两种数据的数字数据流的电路和方法，以便仅保留接收机所需的数字数据流的那些部分。 在一个特定应用中，这种接收机用在具有数字机顶盒接收机的电视系统中。 第一控制电路从数字数据流中的输入数据包中提取分组标识符，并根据输入数据分组是第一类还是第二类产生信号。 在第二控制电路的控制下，与第一类型的数据分组相关联并且由接收机所要求的信息集存储在存储器中。 响应于接收到第一类型的输入数据分组的第三控制电路确定输入数据分组的至少一部分是否与存储的信息组匹配，并且响应于此设置匹配信号。

公开(公告)号：US20030056164A1

公开(公告)日：2003-03-20

申请号：US09954637

申请日：2001-09-14

Applicant: STMicroelectronics Limited

Inventor： Christophe Lauga

IPC: G01R031/28

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/318572

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract translation: 包括测试扫描装置的半导体集成电路具有成对布置的多个扫描链。 这些扫描链具有用于接收测试图案的输入端子，以及提供给诸如分布式异或树多输入移位寄存器之类的压缩逻辑的输出，以提供作为从输出测试图案导出的压缩信号的输出。 在替代配置中，每对的第一扫描链连接到每对的第二扫描链，并且第二扫描链的输入端变为输出端。 从而创建第一和第二扫描链的更长的扫描链以及一个输入端和一个输出端。 两个负载允许在第一模式下进行有效的扫描，或者调试以确定第二模式中故障的位置。

公开(公告)号：US20020196710A1

公开(公告)日：2002-12-26

申请号：US10157731

申请日：2002-05-29

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Paul Elliott

IPC: G06F001/04 ,  G04F005/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 开关请求信号相对于时钟A首先被重新定时以给出信号P，相对于时钟B被重新定时以给出信号Q，并且最后相对于时钟A被重新定时以给出信号R.选择器电路操作使得当 信号Q被置位，当第二时钟信号B被输出时，当由或非门组合的信号P和信号R都不被断言时，输出第一时钟信号A，并且在其它时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。

公开(公告)号：US20020191725A1

公开(公告)日：2002-12-19

申请号：US10106899

申请日：2002-03-25

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03D003/24

CPC classification number: H03D13/004

Abstract: A digital phase comparator circuit that determines and adjusts the relative phase of two digital clock signals derived from the same digital clock. The circuit having two inputs, one connected to receive each of the clock signals to be compared and including a latch circuit to receive one clock signal at the clock input, and the other clock signal at a data input. The latch circuit is arranged so that the output is equal to the signal at the data input when measured at the clock edge. The output is therefore a logic null1null when the second clock leads the first clock, and a logic null0null when the second clock lags the first clock.

Abstract translation: 数字相位比较器电路，用于确定并调整从相同数字时钟导出的两个数字时钟信号的相对相位。 该电路具有两个输入端，一个连接到接收要比较的每个时钟信号，并且包括用于在时钟输入端接收一个时钟信号的锁存电路，以及数据输入端的另一个时钟信号。 锁存电路被布置为使得当在时钟边沿测量时，输出等于数据输入端的信号。 因此，当第二个时钟引导第一个时钟时，输出为逻辑“1”，当第二个时钟延迟第一个时钟时，输出为逻辑“0”。