CHIP PACKAGE WITH ESD PROTECTION STRUCTURE
    131.
    发明申请
    CHIP PACKAGE WITH ESD PROTECTION STRUCTURE 审中-公开
    具有ESD保护结构的芯片封装

    公开(公告)号:US20100001394A1

    公开(公告)日:2010-01-07

    申请号:US12167703

    申请日:2008-07-03

    CPC classification number: H01L23/60 H01L2924/0002 H01L2924/00

    Abstract: A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced.

    Abstract translation: 芯片封装包括半导体芯片,耦合到半导体芯片的多个引脚以及被配置为在引脚之间形成电连接的导电结构,其中电连接被配置为当芯片封装插入插座时被禁用 。 由于引脚通过导电结构电连接,因ESD事件发生时,由ESD事件引起的浪涌电流可分配给所有引脚而不是单引脚。 因此,连接到引脚的所有ESD保护电路可用于在ESD事件期间耗散浪涌电流,并且可以显着降低由ESD引起的电路损坏。

    Time counting assembly with a display for world time zones
    132.
    发明授权
    Time counting assembly with a display for world time zones 失效
    具有世界时区显示的计时装配

    公开(公告)号:US07639568B2

    公开(公告)日:2009-12-29

    申请号:US11783899

    申请日:2007-04-12

    Applicant: Wen-Chun Lin

    Inventor: Wen-Chun Lin

    CPC classification number: G04G9/0076 G04B19/223

    Abstract: A time counting assembly with a display for world time zones includes a power source, a second counter, a minute counter, an hour counter, and a time zone display for displaying a correct time over a faceplate. Stirring the time zone adjustable ring with the hand ultimately turns a hour hand to the time in accordance with the time zone corresponding to a second landmark.

    Abstract translation: 具有用于世界时区的显示器的时间计数组件包括电源,第二计数器,分钟计数器,小时计数器和用于在面板上显示正确时间的时区显示。 根据与第二个地标对应的时区,用手搅拌时区可调节环最终会转动一小时的时间。

    Method of cleaning wafer after etching process
    133.
    发明授权
    Method of cleaning wafer after etching process 有权
    蚀刻工艺后的晶圆清洗方法

    公开(公告)号:US07628866B2

    公开(公告)日:2009-12-08

    申请号:US11562989

    申请日:2006-11-23

    Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.

    Abstract translation: 提供了在蚀刻处理之后清洁晶片的方法。 提供了具有蚀刻停止层,电介质层,依次形成的图案化金属硬掩模的基板。 使用图案化金属硬掩模,在介电层中限定开口。 开口露出一部分蚀刻停止层。 在氦气的环境中进行干蚀刻处理以除去由开口露出的蚀刻停止层。 使用氮和氢的混合物作为反应气体在晶片表面上进行干洗处理。 使用含有微量氢氟酸的清洗溶液在晶片表面上进行湿式清洗处理。

    CLADDING GRATING AND FIBER SIDE-COUPLING APPARATUS USING THE SAME
    134.
    发明申请
    CLADDING GRATING AND FIBER SIDE-COUPLING APPARATUS USING THE SAME 审中-公开
    使用相同的粘合剂和纤维侧连接装置

    公开(公告)号:US20090285528A1

    公开(公告)日:2009-11-19

    申请号:US12266920

    申请日:2008-11-07

    CPC classification number: G02B6/02061

    Abstract: A fiber side-coupling apparatus can be spliced with active fiber as a fiber-based side-coupler in series at both sides for distributively-pumped monolithic fiber lasers. This side-coupling apparatus includes a large-mode-area double-clad passive optical fiber. A cladding grating, formed on the cladding surface of the passive fiber, comprises a plurality of grating members and a reflection layer formed thereon. A laser diode bar array is disposed on one side of the optical fiber opposite the cladding grating. A collimation device, placed between the optical fiber and the laser diode bar array, is used to collect the pump beam to the cladding grating as much as possible in fast axis and collimate the pump beam to be incident to the cladding grating in slow axis as normally as possible. The collimated pump beams emitted from a laser diode bar array are normally incident to the cladding grating within the alignment tolerance of ±2 to ±4 degrees. Without the reentrance loss effect, the pump beams diffracted and reflected by the cladding grating propagates in the inner cladding of the passive fiber due to total internal reflection. In one embodiment, the grating member can be a binary or blazed cross section.

    Abstract translation: 纤维侧耦合装置可以用作为分布式泵浦单片光纤激光器的两侧串联的基于光纤的侧耦合器的有源光纤进行接合。 该侧耦合装置包括大模式双重双层无源光纤。 形成在被动光纤的包层表面上的包层光栅包括多个光栅部件和形成在其上的反射层。 激光二极管棒阵列设置在与包层光栅相对的光纤的一侧上。 放置在光纤和激光二极管棒阵列之间的准直装置用于尽可能快地将泵浦光束收集到包层光栅,并准直泵浦光束以慢轴入射到包层光栅,如 通常可能。 从激光二极管棒阵列发射的准直泵浦光束通常在±2至±4度的对准公差内入射到包层光栅。 没有折返损耗效应,由包层光栅衍射和反射的泵浦光由于全内反射而在无源光纤的内包层中传播。 在一个实施例中,光栅构件可以是二进制或闪耀的横截面。

    Light-emitting keyboard
    135.
    发明申请
    Light-emitting keyboard 失效
    发光键盘

    公开(公告)号:US20090283393A1

    公开(公告)日:2009-11-19

    申请号:US12314801

    申请日:2008-12-17

    CPC classification number: G06F3/0202

    Abstract: The present invention is related to a light-emitting keyboard, comprising: a light guide having a light entrance surface, a bottom surface and a light exit surface; a light source provided adjacent to the light entrance surface of the light guide; a first reflector disposed underneath the bottom surface of the light guide to reflect the light originated from the light source to enter into said light guide; a second reflector disposed on top of said light exit surface of the light guide; a membrane circuit board disposed on top of said second reflector, said membrane circuit board being provided with an elastic member; a supporting plate disposed on top of the membrane circuit board; a scissor assembly engaged with said supporting plate and provided thereon; and a keycap supported by said scissor assembly.

    Abstract translation: 本发明涉及一种发光键盘,包括:具有光入射表面,底表面和光出射表面的光导; 设置在所述光导入口的光入射面附近的光源; 设置在所述光导的底面下方的第一反射体,以反射来自所述光源的光进入所述导光体; 设置在所述光导的所述光出射表面的顶部的第二反射器; 设置在所述第二反射器的顶部的膜电路板,所述膜电路板设置有弹性构件; 设置在所述膜电路板的顶部的支撑板; 与所述支撑板接合并设置在其上的剪刀组件; 和由所述剪刀组件支撑的键帽。

    LED lamp
    136.
    发明授权
    LED lamp 失效
    点灯

    公开(公告)号:US07611264B1

    公开(公告)日:2009-11-03

    申请号:US12200267

    申请日:2008-08-28

    Abstract: A LED lamp includes a main body surrounded by a fin assembly on the periphery at an upper side and a lower side, a power supply holder located at the upper side and a plurality of LED lamp assemblies located at the lower side. The LED lamp assemblies are encased by a light converging plate which is further encased by a transparent lamp shade fastening to the lower side of the main body. The LED lamp thus formed may be fastened to a ceiling for indoor use through an upper cap of a fastening assembly, or an outdoor electric wire pole through a fastening tray. Each of the LED lamp assemblies has a heat transfer tube to transfer the generated heat to the main body for dispersing through the fin assembly. Thus desired heat dissipation can be accomplished.

    Abstract translation: 一种LED灯包括在上侧和下侧的外围由翅片组件围绕的主体,位于上侧的电源保持器和位于下侧的多个LED灯组件。 LED灯组件被聚光板包围,该聚光板进一步被固定在主体下侧的透明灯罩遮蔽。 如此形成的LED灯可以通过紧固组件的上盖或通过紧固托盘的室外电线杆紧固到用于室内的天花板。 每个LED灯组件具有传热管,以将产生的热量传递到主体以通过翅片组件分散。 因此可以实现期望的散热。

    ERROR DETECTION METHOD FOR A COMPUTER SYSTEM, AND ELECTRONIC DEVICE
    137.
    发明申请
    ERROR DETECTION METHOD FOR A COMPUTER SYSTEM, AND ELECTRONIC DEVICE 审中-公开
    计算机系统的误差检测方法和电子设备

    公开(公告)号:US20090265580A1

    公开(公告)日:2009-10-22

    申请号:US12354315

    申请日:2009-01-15

    CPC classification number: G06F11/2289

    Abstract: An error detection method for a computer system includes the steps of: enabling an error-detecting computer to communicate with a keyboard controller of a computer-under-test through a communication interface; enabling the error-detecting computer to issue an error detection command to the keyboard controller that causes the keyboard controller to issue a request command to the basic input/output system (BIOS) of the computer-under-test; enabling the BIOS, in response to the request command, to access the keyboard controller and determine hardware status information that is being requested from the error detection command, and subsequently, to obtain the hardware status information of the computer-under-test, and to transmit the hardware status information to the keyboard controller; and enabling the keyboard controller to transmit the hardware status information received thereby to the error-detecting computer through the communication interface.

    Abstract translation: 一种用于计算机系统的错误检测方法,包括以下步骤:使得错误检测计算机能够通过通信接口与被测计算机的键盘控制器进行通信; 使得错误检测计算机向键盘控制器发出错误检测命令,使键盘控制器向被测电脑的基本输入/输出系统(BIOS)发出请求命令; 使得BIOS响应于请求命令访问键盘控制器并且从错误检测命令中确定正在请求的硬件状态信息,并且随后获得待测计算机的硬件状态信息,以及 将硬件状态信息发送到键盘控制器; 并且使得键盘控制器能够通过通信接口将由此接收到的硬件状态信息发送到错误检测计算机。

    Disconnected DPW Structures for Improving On-State Performance of MOS Devices
    138.
    发明申请
    Disconnected DPW Structures for Improving On-State Performance of MOS Devices 有权
    断开的DPW结构,以改善MOS器件的状态性能

    公开(公告)号:US20090256200A1

    公开(公告)日:2009-10-15

    申请号:US12103524

    申请日:2008-04-15

    Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending from over the first HVW region to over the second HVW region; a gate electrode on the gate dielectric; a drain region in the second HVW region; a source region at an opposite side of the gate dielectric than the drain region; and a deep well region of the first conductivity type underlying the second HVW region. Substantially no deep well region is formed directly underlying the drain region.

    Abstract translation: 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱(HVW)区域; 第二导电类型的第二HVW区域与第一导电类型相反,覆盖在衬底上并横向邻接第一HVW区域; 从第一HVW区域延伸到第二HVW区域上方的栅极电介质; 栅电极上的栅电极; 第二HVW区域中的漏极区域; 栅极电介质的与漏极区相反的一侧的源极区; 以及位于第二HVW区域下方的第一导电类型的深阱区域。 基本上没有深沟区直接形成在漏极区下面。

    High voltage semiconductor devices and methods for fabricating the same
    139.
    发明授权
    High voltage semiconductor devices and methods for fabricating the same 有权
    高压半导体器件及其制造方法

    公开(公告)号:US07602037B2

    公开(公告)日:2009-10-13

    申请号:US11692213

    申请日:2007-03-28

    Abstract: An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.

    Abstract translation: 能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。 具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。 在阱区内,掺杂体区域包括在栅叠层的一部分下延伸的沟道区,漂移区与沟道区相邻。 漏极区域在漂移区域内并与其第一侧隔开距离,并且源极区域在其第二侧附近的掺杂体区域内。 在掺杂体区和阱区之间不存在P-N结。

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