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131.
公开(公告)号:US20180247200A1
公开(公告)日:2018-08-30
申请号:US15753666
申请日:2016-08-18
Applicant: D-Wave Systems Inc.
Inventor: Jason Rolfe
CPC classification number: G06N3/086 , G06N3/0445 , G06N3/0454 , G06N3/0472 , G06N3/08 , G06N3/084 , G06N3/088 , G06N10/00
Abstract: A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior.
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公开(公告)号:US10037493B2
公开(公告)日:2018-07-31
申请号:US14520139
申请日:2014-10-21
Applicant: D-Wave Systems Inc.
Inventor: Richard G. Harris , Mohammad H. S. Amin , Anatoly Smirnov
IPC: G06F17/00 , G06N99/00 , H03K3/38 , H03K19/195 , G11C11/44
CPC classification number: G06N10/00 , G11C11/44 , H03K3/38 , H03K19/1952
Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.
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公开(公告)号:US20180196780A1
公开(公告)日:2018-07-12
申请号:US15870411
申请日:2018-01-12
Applicant: D-Wave Systems Inc.
Inventor: Mohammad H. Amin , Evgeny A. Andriyash
CPC classification number: G06F17/17 , G06F5/01 , G06F9/30145 , G06F17/13 , G06F17/18 , G06N7/005 , G06N10/00 , H04L9/0852
Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.
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公开(公告)号:US09984333B2
公开(公告)日:2018-05-29
申请号:US14860087
申请日:2015-09-21
Applicant: D-Wave Systems Inc.
Inventor: Jacob Daniel Biamonte , Andrew J. Berkley , Mohammad H.S. Amin
CPC classification number: G06N99/002 , B82Y10/00 , G06N99/00 , Y10S977/933
Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.
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135.
公开(公告)号:US20180101786A1
公开(公告)日:2018-04-12
申请号:US15726239
申请日:2017-10-05
Applicant: D-WAVE SYSTEMS INC.
Inventor: Kelly T. R. Boothby
CPC classification number: G06N10/00 , H01L39/02 , H01L39/22 , H01L39/223 , H03M1/1009 , H03M1/66
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号:US09870277B2
公开(公告)日:2018-01-16
申请号:US14778478
申请日:2014-02-05
Applicant: D-Wave Systems Inc.
Inventor: Andrew J. Berkley
CPC classification number: G06F11/0724 , G06F11/10 , G06F11/1492 , G06N99/002
Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.
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公开(公告)号:US20170373658A1
公开(公告)日:2017-12-28
申请号:US15672506
申请日:2017-08-09
Applicant: D-Wave Systems Inc.
Inventor: Murray C. Thom , Alexander M. Tcaciuc , Gordon Lamont , J. Craig Petroff , Richard D. Neufeld , David S. Bruce , Sergey V. Uchaykin
CPC classification number: H03H1/00 , H01F6/06 , H01F6/065 , H01F27/2823 , H01F41/048 , H01F41/069 , H01F41/076 , H01L39/02 , H01L39/14 , H01P1/203 , H03H7/0115 , H03H7/0138 , H03H7/1741 , H03H2001/0078
Abstract: Systems and devices for providing differential input/output communication with a superconducting device are described. Each differential I/O communication is electrically filtered using a respective tubular filter structure incorporating superconducting lumped element devices and high frequency dissipation by metal powder epoxy. A plurality of such tubular filter structures is arranged in a cryogenic, multi-tiered assembly further including structural/thermalization supports and a device sample holder assembly for securing a device sample, for example a superconducting quantum processor. The interface between the cryogenic tubular filter assembly and room temperature electronics is achieved using hermetically sealed vacuum feed-through structures designed to receive flexible printed circuit board cable.
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公开(公告)号:US09762200B2
公开(公告)日:2017-09-12
申请号:US14959846
申请日:2015-12-04
Applicant: D-Wave Systems Inc.
Inventor: Murray C. Thom , Alexander M. Tcaciuc
IPC: H03H7/01 , H01P1/20 , H03H1/00 , H01L39/14 , H01P1/203 , H01L39/02 , H01F27/28 , H01F41/04 , H01F41/06 , H01F6/06
CPC classification number: H03H1/00 , H01F6/06 , H01F6/065 , H01F27/2823 , H01F41/048 , H01F41/069 , H01F41/076 , H01L39/02 , H01L39/14 , H01P1/203 , H03H7/0115 , H03H7/0138 , H03H7/1741 , H03H2001/0078
Abstract: Systems and devices for providing differential input/output communication with a superconducting device are described. Each differential I/O communication is electrically filtered using a respective tubular filter structure incorporating superconducting lumped element devices and high frequency dissipation by metal powder epoxy. A plurality of such tubular filter structures is arranged in a cryogenic, multi-tiered assembly further including structural/thermalization supports and a device sample holder assembly for securing a device sample, for example a superconducting quantum processor. The interface between the cryogenic tubular filter assembly and room temperature electronics is achieved using hermetically sealed vacuum feed-through structures designed to receive flexible printed circuit board cable.
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公开(公告)号:US20170255871A1
公开(公告)日:2017-09-07
申请号:US15452438
申请日:2017-03-07
Applicant: D-Wave Systems Inc.
Inventor: William G. Macready , Firas Hamze , Fabian A. Chudak , Mani Ranjbar , Jack R. Raymond , Jason T. Rolfe
Abstract: A hybrid computer comprising a quantum processor can be operated to perform a scalable comparison of high-entropy samplers. Performing a scalable comparison of high-entropy samplers can include comparing entropy and KL divergence of post-processed samplers. A hybrid computer comprising a quantum processor generates samples for machine learning. The quantum processor is trained by matching data statistics to statistics of the quantum processor. The quantum processor is tuned to match moments of the data.
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140.
公开(公告)号:US20170255629A1
公开(公告)日:2017-09-07
申请号:US15448361
申请日:2017-03-02
Applicant: D-Wave Systems Inc.
Inventor: Murray C. Thom , Aidan P. Roy , Fabian A. Chudak , Zhengbing Bian , William G. Macready , Robert B. Israel , Tomas J. Boothby , Sheir Yarkoni , Yanbo Xue , Dmytro Korenkevych
CPC classification number: G06N10/00
Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
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