公开(公告)号：US20090300852A1

公开(公告)日：2009-12-10

申请号：US12470804

申请日：2009-05-22

Applicant: Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

Inventor： Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

IPC: D06F33/00 ,  D06F39/00

CPC classification number: D06F35/007 ,  D06F37/203

Abstract: The present invention relates to a washing machine and a method of controlling a washing machine. According to the washing machine and the method of controlling the washing machine in accordance with the present invention, the drum is operated at a first speed so that laundry tumbles within the drum. A laundry amount within the drum during the first speed operation is sensed. The drum is driven at a second speed so that part of the laundry tumbles within the drum and another part of the laundry adheres to the drum. Operation commands for driving the drum subsequent to the first speed operation are changed based on the sensed laundry amount. Accordingly, at the time of a dehydration cycle, stability of the washing machine and laundry balancing can be ensured.

Abstract translation: 本发明涉及洗衣机和洗衣机的控制方法。 根据本发明的洗衣机和洗衣机的控制方法，以第一速度操作滚筒，使得衣物滚筒内滚动。 感测在第一速度操作期间滚筒内的衣物量。 鼓以第二速度被驱动，使得衣物的一部分在滚筒内滚动，另一部分衣物粘附到滚筒上。 基于感测到的衣物量改变用于在第一速度操作之后驱动滚筒的操作命令。 因此，在脱水循环时，可以确保洗衣机的稳定性和衣物平衡。

公开(公告)号：US20090279378A1

公开(公告)日：2009-11-12

申请号：US12164797

申请日：2008-06-30

Applicant: Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

Inventor： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

IPC: G11C8/18

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C7/225

Abstract: A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

Abstract translation: 一种半导体存储器件，包括用于接收源时钟并将产生的时钟提供给多个时钟传输线的时钟输入; 多个时钟放大器，每个时钟放大器响应于列使能信号放大加载在所述多个时钟传输线中的一个上的相应的生成时钟; 以及用于响应于由多个时钟放大器输出的放大时钟而输入/输出多个数据的数据输入/输出。

公开(公告)号：US07567483B2

公开(公告)日：2009-07-28

申请号：US11819801

申请日：2007-06-29

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/222

Abstract: A semiconductor memory device includes a first clock input unit for generating a first clock signal based on a signal at an intersection of a system clock signal and an inverted system clock signal; a second input unit for generating a second clock signal based on a signal at an intersection of the system clock signal and a reference signal; a third input unit for generating a third clock signal based on a signal at an intersection of the inverted system clock signal and the reference signal; a delay unit for generating a delay clock signal by delaying the first clock signal in response to a delay control signal; and a clock delay control unit for generating the delay control signal in response to a phase difference between the second clock signal and the delay clock signal or a phase difference between the third clock signal and the delay clock signal.

Abstract translation: 半导体存储器件包括：第一时钟输入单元，用于基于系统时钟信号和反相系统时钟信号的交点处的信号产生第一时钟信号; 第二输入单元，用于基于系统时钟信号和参考信号的交点处的信号产生第二时钟信号; 第三输入单元，用于基于反相系统时钟信号和参考信号的交点处的信号产生第三时钟信号; 延迟单元，用于通过响应于延迟控制信号延迟所述第一时钟信号来产生延迟时钟信号; 以及时钟延迟控制单元，用于响应于第二时钟信号和延迟时钟信号之间的相位差或第三时钟信号和延迟时钟信号之间的相位差产生延迟控制信号。

公开(公告)号：US20090175116A1

公开(公告)日：2009-07-09

申请号：US12165045

申请日：2008-06-30

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kum Yoon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kum Yoon

IPC: G11C8/18 ,  H03L7/06

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  H03K2005/00208 ,  H03L7/0805 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/24

Abstract: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

Abstract translation: 一种具有时钟同步电路的半导体存储器件，其能够执行期望的相位/频率锁定操作，而没有抖动峰化现象和使用注入锁定的振荡控制电压信号的模式抖动。 该装置包括锁相环，其检测反馈时钟信号和参考时钟信号之间的相位/频率差，以产生对应于检测到的相位/频率差的振荡控制电压信号，并产生对应于 振荡控制电压信号。 注入锁定振荡单元响应于振荡控制电压信号建立自由运行频率，并产生与参考时钟信号同步的内部时钟信号。

公开(公告)号：US20090168546A1

公开(公告)日：2009-07-02

申请号：US12154936

申请日：2008-05-28

Applicant: Kyung-Hoon Kim ,  Sang-Sic Yoon

Inventor： Kyung-Hoon Kim ,  Sang-Sic Yoon

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

Abstract: A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with the second clock to output a buffered second clock having the same frequency as the first clock, a data output circuit configured to output an internal data in response to the buffered second clock, a delay unit configured to delay the buffered second clock by a predetermined time, and a phase detector configured to detect a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and to output the detection result.

Abstract translation: 半导体存储器件包括：第一缓冲单元，被配置为缓冲用于地址信号的第一时钟和与第一时钟同步地输入的命令;第二缓冲单元，被配置为缓冲第二时钟以使数据信号同步 第二时钟输出具有与第一时钟相同频率的缓冲的第二时钟，数据输出电路被配置为响应于所缓冲的第二时钟输出内部数据;延迟单元，被配置为将缓冲的第二时钟延迟预定的 时间，以及相位检测器，被配置为检测延迟单元的输出时钟和第一缓冲单元的输出时钟的相位差，并输出检测结果。

公开(公告)号：US20090116331A1

公开(公告)日：2009-05-07

申请号：US12006121

申请日：2007-12-31

Applicant: Kyung-Hoon Kim ,  Sang-Sik Yoon

Inventor： Kyung-Hoon Kim ,  Sang-Sik Yoon

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock.

Abstract translation: 半导体存储器件及其操作方法包括：相位检测单元，被配置为比较第一参考时钟的相位和第二分频基准时钟的相位，以输出比较结果信号;相位控制和分频单元，被配置为产生 根据从相位检测单元输出的比较结果信号，将第二参考时钟除以预定比例，并调整第二参考时钟的相位，来分配第二分频参考时钟。

公开(公告)号：US20090058481A1

公开(公告)日：2009-03-05

申请号：US12005879

申请日：2007-12-28

Applicant: Kyung-Hoon Kim ,  Jun-Woo Lee ,  Taek-Sang Song

Inventor： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Taek-Sang Song

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  H03K5/1534

Abstract: A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180° phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock.

Abstract translation: 半导体存储器件具有占空比校正电路，该电路能够输出占空比校正时钟及其倒相时钟，它们之间具有基本精确的180°相位差。 半导体存储器件包括占空比校正器，其被配置为接收第一时钟和第二时钟以产生第一输出时钟和响应校正信号校正其占空比的第二输出时钟;以及时钟沿检测器，被配置为产生 所述校正信号对应于所述第一输出时钟的参考转换定时与所述第二输出时钟的参考转换定时之间的间隔。

公开(公告)号：US20090045857A1

公开(公告)日：2009-02-19

申请号：US12255056

申请日：2008-10-21

Applicant: Kyung-Hoon KIM

Inventor： Kyung-Hoon KIM

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805 ,  H03L7/087

Abstract: A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Abstract translation: 延迟锁定环通过使用具有比DLL输出时钟更高级的相位的输出时钟来增加延迟锁定环的操作余量。 时钟延迟补偿块接收外部时钟信号从而产生第一多时钟和第二多时钟。 相位控制块将第一多时钟与第二多个时钟进行比较，以产生控制移位操作的相位控制信号。 多相延迟控制块基于相位控制信号执行移位操作，以控制时钟延迟补偿块。

公开(公告)号：US07489172B2

公开(公告)日：2009-02-10

申请号：US11478082

申请日：2006-06-30

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/00 ,  H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805

Abstract: A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a count a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.

Abstract translation: 延迟锁定环（DLL）驱动器控制电路能够通过防止不必要的时钟的输出来减少电流消耗量。 DLL驱动器控制电路包括用于驱动DLL时钟的DLL驱动器和用于产生用于响应于具有与活动模式相关联的信息的信号来控制DLL驱动程序的操作的DLL驱动器控制器。 DLL驱动器控制器设置有用于对DLL时钟进行计数以产生具有多个位的设置值的计数器，并且如果两个值相同则产生激活的等信号;以及SR锁存器，用于接受相等的信号和 所述信号具有与所述活动模式相关联的信息以提供所述控制信号。

公开(公告)号：US07449927B2

公开(公告)日：2008-11-11

申请号：US11478191

申请日：2006-06-30

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0805 ,  H03L7/087

Abstract: A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Abstract translation: 延迟锁定环通过使用具有比DLL输出时钟更高级的相位的输出时钟来增加延迟锁定环的操作余量。 时钟延迟补偿块接收外部时钟信号从而产生第一多时钟和第二多时钟。 相位控制块将第一多时钟与第二多个时钟进行比较，以产生控制移位操作的相位控制信号。 多相延迟控制块基于相位控制信号执行移位操作，以控制时钟延迟补偿块。