公开(公告)号：US11573849B2

公开(公告)日：2023-02-07

申请号：US17236445

申请日：2021-04-21

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US11567695B2

公开(公告)日：2023-01-31

申请号：US17575524

申请日：2022-01-13

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

公开(公告)号：US20230021898A1

公开(公告)日：2023-01-26

申请号：US17857241

申请日：2022-07-05

Applicant: Rambus Inc.

Inventor： Aws SHALLAL ,  Chen CHEN

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16

Abstract: A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.

公开(公告)号：US11556164B2

公开(公告)日：2023-01-17

申请号：US17117388

申请日：2020-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/06 ,  G06F1/32 ,  G06F9/38 ,  G06F12/0855 ,  G06F13/36

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US20230009384A1

公开(公告)日：2023-01-12

申请号：US17852165

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/06 ,  H01L25/065

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US11552748B2

公开(公告)日：2023-01-10

申请号：US17386111

申请日：2021-07-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L1/24 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C29/02 ,  G11C7/10 ,  H04L27/00 ,  G11C7/04 ,  H04L7/033

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US11551735B2

公开(公告)日：2023-01-10

申请号：US15555470

申请日：2016-03-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt

IPC: G11C11/00 ,  G11C5/04 ,  G11C5/06 ,  G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C7/12

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

公开(公告)号：US20220417067A1

公开(公告)日：2022-12-29

申请号：US17852922

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Richelle L. Smith ,  Carl W. Werner

IPC: H04L27/233 ,  H04L27/34 ,  H04L27/20

Abstract: A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.

公开(公告)号：US11537531B2

公开(公告)日：2022-12-27

申请号：US17115505

申请日：2020-12-08

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Trung A. Diep

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/0802 ,  G06F12/1009

Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

公开(公告)号：US20220407749A1

公开(公告)日：2022-12-22

申请号：US17852278

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

IPC: H04L25/03

Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.