公开(公告)号：US20020095637A1

公开(公告)日：2002-07-18

申请号：US10097785

申请日：2002-03-14

Applicant: STMicroelectronics S.A.

Inventor： Jean-Marie Gaultier

IPC: H04L001/18 ,  G08C025/02

CPC classification number: H04L29/06 ,  H04L1/1803 ,  H04L69/324

Abstract: A method for communicating between a transmitting unit and a receiving unit. A messages formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device, means for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device. The reception bit (or bits) indicates the elementary message that is to be transmitted next by the transmitting unit. In one preferred embodiment, the transmitter transmits at least two reception bits whose values indicate the elementary message that is to be transmitted next by the transmitting unit.

Abstract translation: 一种用于在发送单元和接收单元之间进行通信的方法。 由基本消息形成的消息从发送单元发送到接收单元，并且至少一个接收位从接收单元发送到发送单元。 接收位（或比特）允许发送单元确定接下来要发送的基本消息。 在优选方法中，从接收单元发送至少两个接收比特，并且接收比特的值表示发送单元将要发送的基本消息。 本发明还提供一种用于从发送装置接收消息的接收装置。 接收装置包括用于从发送装置接收发送的消息的接口，用于分析接收到的基本消息以确定其是否被正确接收的装置，以及用于向发送装置发送至少一个接收比特的发送机。 接收位（或位）表示发送单元接下来要发送的基本消息。 在一个优选实施例中，发射机发送至少两个接收位，其值表示发送单元将要发送的基本消息。

公开(公告)号：US20020090781A1

公开(公告)日：2002-07-11

申请号：US10042506

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Catherine Mallardeau

IPC: H01L021/8242

CPC classification number: H01L27/1087 ,  H01L27/10832

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of Nnull doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

Abstract translation: 通过从硅衬底外延生长制造DRAM型电池的工艺包括生长硅锗层和硅层; 叠加第一层N +掺杂硅和第二层P掺杂硅; 以及在硅衬底上形成晶体管。 该方法还包括蚀刻晶体管的延伸中的沟槽，以提供在预定深度上相对于硅层访问硅锗层以形成横向空腔，以及在沟槽和侧向空腔中形成电容器 。

公开(公告)号：US20020050610A1

公开(公告)日：2002-05-02

申请号：US09921280

申请日：2001-08-02

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray

IPC: H01L029/788

CPC classification number: H01L29/42324 ,  H01L29/7886

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

Abstract translation: 非易失性存储单元包括具有环形布置并包括浮动栅极的MOS晶体管，环形布置的中心处的中心电极并且围绕浮置栅极，以及沿环形布置的周边的至少一个外围电极。

公开(公告)号：US20020031015A1

公开(公告)日：2002-03-14

申请号：US09952904

申请日：2001-09-13

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  David Naura ,  Sebastien Zink

IPC: G11C005/00

CPC classification number: G11C7/12 ,  G11C16/24

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2pnull2q other data in the 2pnull2q llow-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2pnullqnull1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract translation: 集成电路存储器的列寄存器，特别是在EEPROM技术中，用于将2P位的数据字写入存储器的方法，其中p是非零整数。 该方法包括以下步骤：1）擦除字的所有单元; 2）在qp高压锁存器（HV1，HV3，HV5，HV7）中加载2q数据，并在2p-2q低压锁存器（LV0，LV2，LV4，LV6）中加载2p-2q其他数据; 和3）根据存储在2q高电压锁存器中的数据来编程存储器（M0，M2，M4，M6）的2q个单元; 以及重复2p-q-1次以下步骤：4）在步骤2）中加载2q高电压锁存器中的2q其他数据的2q高电压锁存器; 和5）根据存储在2q高电压锁存器中的数据来编程存储器（M1，M3，M5，M7）的2q个其他单元。

公开(公告)号：US20020018367A1

公开(公告)日：2002-02-14

申请号：US09896817

申请日：2001-06-29

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: G11C016/30

CPC classification number: G11C5/143 ,  G11C16/12

Abstract: An integrated circuit having as power supply voltages a low voltage reference, a logic supply voltage reference and a high voltage reference is provided. The high voltage reference is greater than the low voltage reference and the logic supply voltage reference. The integrated circuit includes an electrically programmable non-volatile memory element, and a selection and programming circuit connected thereto. A voltage control device is connected to a power supply input node of the selection and programming circuit for applying, based upon a programming control signal, the high voltage reference for programming the electrically programmable non-volatile memory element or for applying at least one logic supply voltage reference.

Abstract translation: 提供具有作为电源电压的低电压基准，逻辑电源电压基准和高电压基准的集成电路。 高电压参考值大于低电压参考电压和逻辑电源参考电压。 集成电路包括电可编程非易失性存储器元件以及与其连接的选择和编程电路。 电压控制装置连接到选择和编程电路的电源输入节点，用于基于编程控制信号将用于编程电可编程非易失性存储器元件的高电压参考值或用于施加至少一个逻辑电源 电压参考。

公开(公告)号：US20020012067A1

公开(公告)日：2002-01-31

申请号：US09852962

申请日：2001-05-10

Applicant: STMicroelectronics S.A.

Inventor： Vincent Tauzia

IPC: H04N011/00

CPC classification number: H04N5/44543 ,  H04N7/0882 ,  H04N21/4312 ,  H04N21/4888

Abstract: A teletext program includes several teletext pages, with each teletext page being broadcast in the form of a set of data packets. A method for displaying a teletext program index on a television receiver screen includes receiving a teletext page which includes the set of data packets. The set of data packets includes first and second data packets. The first data packet includes at least one label referring to another teletext page, and the second data packet is associated with the first data packet and includes a page number associated with at least one label. The method includes decoding the first and second data packets to obtain at least one label and the associated page number, and at least one label and the associated page number are stored in a buffer memory.

Abstract translation: 图文电视节目包括几个图文电视页面，每个图文电视页面以一组数据分组的形式进行广播。 一种用于在电视接收机屏幕上显示图文电视节目索引的方法包括接收包括该组数据分组的图文电视页面。 该组数据分组包括第一和第二数据分组。 第一数据分组包括至少一个引用另一图文页面的标签，并且第二数据分组与第一数据分组相关联并且包括与至少一个标签相关联的页码。 该方法包括对第一和第二数据分组进行解码以获得至少一个标签和相关联的页面编号，并且至少一个标签和相关页面编号被存储在缓冲存储器中。

公开(公告)号：US20020004918A1

公开(公告)日：2002-01-10

申请号：US09870121

申请日：2001-05-30

Applicant: STMicroelectronics S.A.

Inventor： Frederic Mathieu ,  Frederic Bard

IPC: G06F011/00

CPC classification number: G06F11/2236 ,  G01R31/31835 ,  G06F11/261

Abstract: A method is for the preparation and execution of a self-test procedure to validate the behavior of a processor model to be tested. The processor model may be a processor or an associated simulator. The method provides self-test procedures that are immediately executable by all the models of a processor and that give OK/ERROR type results that are easy to interpret.

Abstract translation: 一种方法是准备和执行自检程序，以验证要测试的处理器模型的行为。 处理器模型可以是处理器或相关联的模拟器。 该方法提供了可以由处理器的所有型号立即执行的自检程序，并给出易于解释的OK / ERROR类型结果。

公开(公告)号：US20020003586A1

公开(公告)日：2002-01-10

申请号：US09827306

申请日：2001-04-05

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Pierre-Olivier Jouffre ,  Frederic Paillardet

IPC: H04N007/20 ,  H04N005/50

CPC classification number: H03G3/3068 ,  H03G3/3089

Abstract: A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/ amplifier stage being fixed.

Abstract translation: 调谐器包括模拟块，数字块和连接在它们之间的模拟/数字转换级。 模拟模块包括连接到频率转置级上游的第一衰减器/受控增益放大器级。 在初始化阶段计算由调谐器接收的整个信号的总平均功率。 该总计算功率在数字模块中与对应于模拟模块的预定位置所需的最大功率的第一预定参考值进行比较。 调整第一衰减器/放大器级的增益以最小化总计算功率与参考值之间的偏差。 在正常工作阶段，选择所接收信号的通道之一，第一衰减器/放大器级的增益是固定的。

公开(公告)号：US20020003286A1

公开(公告)日：2002-01-10

申请号：US09930084

申请日：2001-08-15

Applicant: STMICROELECTRONICS S.A.

Inventor： Michel Marty ,  Alain Chantre ,  Jorge Regolini

IPC: H01L029/70

CPC classification number: H01L29/66242 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract translation: 垂直双极晶体管包括SiGe异质结基底，其由沉积在围绕本征收集器的上部的侧绝缘区域延伸的氮化硅初始层上的硅层和硅锗叠层形成。 层叠层还在固有收集器的位于形成于初始氮化硅层的窗口内部的表面上延伸。

公开(公告)号：US20010054913A1

公开(公告)日：2001-12-27

申请号：US09891964

申请日：2001-06-26

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: H03K019/20

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract translation: 一种具有数字输出的电子电路，包括闩锁（1），控制组件（2），可吹塑组件（3），连接到公共点（14）的第一输入的逻辑门（4））的自动稳定组件， 在自动稳定组件（1）和可吹塑组件（3）之间，以及连接到电子电路的控制输入（20）的第二输入。 断路器（5）由逻辑门（4）的输出控制并且布置在自动稳定组件（1）和地之间，以及相关联的过程。