公开(公告)号：US08426242B2

公开(公告)日：2013-04-23

申请号：US13076169

申请日：2011-03-30

申请人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

发明人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

IPC分类号： H01L21/06

CPC分类号： H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

摘要翻译： 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

公开(公告)号：US08363463B2

公开(公告)日：2013-01-29

申请号：US12729837

申请日：2010-03-23

申请人： Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

发明人： Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

IPC分类号： G11C11/00

CPC分类号： H01L45/1625 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641

摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.

摘要翻译： 一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布 。 根据不同的晶体学，热学和电学条件以及不同的相变条件，使用非恒定浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

公开(公告)号：US08330137B2

公开(公告)日：2012-12-11

申请号：US13084088

申请日：2011-04-11

申请人： Alejandro G. Schrott ,  Chung H. Lam ,  Eric A. Joseph ,  Matthew J. Breitwisch ,  Roger W. Cheek

发明人： Alejandro G. Schrott ,  Chung H. Lam ,  Eric A. Joseph ,  Matthew J. Breitwisch ,  Roger W. Cheek

IPC分类号： H01L47/00 ,  H01L29/04

CPC分类号： H01L45/1625 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1666

摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

摘要翻译： 提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。

公开(公告)号：US08324605B2

公开(公告)日：2012-12-04

申请号：US12286874

申请日：2008-10-02

申请人： Hsiang-Lan Lung ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

发明人： Hsiang-Lan Lung ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

摘要翻译： 使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。 具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。 该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。 导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。 此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

公开(公告)号：US20120276688A1

公开(公告)日：2012-11-01

申请号：US13546684

申请日：2012-07-11

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/06

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20120139119A1

公开(公告)日：2012-06-07

申请号：US13369655

申请日：2012-02-09

申请人： Matthew J. Breitwisch

发明人： Matthew J. Breitwisch

IPC分类号： H01L29/45

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/16

摘要： A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access circuitry, forming a dielectric cap layer over exposed portions of the dielectric layer and the conductive contacts, depositing a planarizing material over the dielectric cap layer, etching a via to an upper surface of each conductive contact, removing the planarizing material, depositing electrode material over the dielectric cap layer and within the vias, the electrode material contacting an upper surface of each conductive contact, and planarizing the electrode material to form a lower bottom electrode over each conductive contact.

摘要翻译： 一种制造用于存储元件的下底电极和具有该下电极的半导体结构的方法包括在半导体衬底上形成介电层，该半导体衬底具有形成在其中的多个导电触点，以连接到存取电路， 介电层和导电触点的部分，在介电覆盖层上沉积平坦化材料，将通孔蚀刻到每个导电接触的上表面，去除平坦化材料，在电介质盖层上方和通孔内沉积电极材料， 所述电极材料接触每个导电接触件的上表面，并且平坦化所述电极材料以在每个导电接触件上形成下部底部电极。

公开(公告)号：US20120126194A1

公开(公告)日：2012-05-24

申请号：US13364153

申请日：2012-02-01

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。

公开(公告)号：US20120115302A1

公开(公告)日：2012-05-10

申请号：US13350817

申请日：2012-01-16

申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Alejandro G. Schrott ,  Yu Zhu

发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Alejandro G. Schrott ,  Yu Zhu

IPC分类号： H01L21/20

CPC分类号： H01L45/144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1683

摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.

摘要翻译： 存储单元结构和形成这种结构的方法。 该方法部分地包括在底部电极的中心上形成氧化层内的通孔。 该方法包括沿通孔的侧壁沉积通孔间隔物并氧化通孔间隔物。 通孔间隔件由具有至少一个半的起珠床比的材料组成，并且当被氧化时是绝缘体。 在氧化期间通孔间隔物的膨胀减小了通孔面积。 或者，该方法部分地包括在底部电极的中心之上在第一层内形成通孔。 第一层具有至少一个半的Pilling-Bedworth比，并且当被氧化时是绝缘体。 该方法还包括在第一层中氧化通孔的侧壁的至少一部分。

公开(公告)号：US20120112154A1

公开(公告)日：2012-05-10

申请号：US13350967

申请日：2012-01-16

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Alejandro G. Schrott

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Alejandro G. Schrott

IPC分类号： H01L47/00

CPC分类号： H01L45/143 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.

摘要翻译： 一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面 沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面 每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极 。

公开(公告)号：US08129268B2

公开(公告)日：2012-03-06

申请号：US12619375

申请日：2009-11-16

申请人： Matthew J. Breitwisch

发明人： Matthew J. Breitwisch

IPC分类号： H01L21/4763

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/16

摘要： A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access circuitry, forming a dielectric cap layer over exposed portions of the dielectric layer and the conductive contacts, depositing a planarizing material over the dielectric cap layer, etching a via to an upper surface of each conductive contact, removing the planarizing material, depositing electrode material over the dielectric cap layer and within the vias, the electrode material contacting an upper surface of each conductive contact, and planarizing the electrode material to form a lower bottom electrode over each conductive contact.

摘要翻译： 一种制造用于存储元件的下底电极和具有该下电极的半导体结构的方法包括在半导体衬底上形成介电层，该半导体衬底具有形成在其中的多个导电触点，以连接到存取电路， 介电层和导电触点的部分，在介电覆盖层上沉积平坦化材料，将通孔蚀刻到每个导电接触的上表面，去除平坦化材料，在电介质盖层上方和通孔内沉积电极材料， 所述电极材料接触每个导电接触件的上表面，并且平坦化所述电极材料以在每个导电接触件上形成下部底部电极。