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    PHASE CHANGE MEMORY CODING
    5.
    发明申请
    PHASE CHANGE MEMORY CODING 有权
    相变存储器编码

    公开(公告)号：US20110317480A1

    公开(公告)日：2011-12-29

    申请号：US12823508

    申请日：2010-06-25

    申请人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    发明人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    IPC分类号： G11C11/00 ,  H01L21/06

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

    摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

    摘要翻译： 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

    Phase change memory coding
    6.
    发明授权
    Phase change memory coding 有权
    相变存储器编码

    公开(公告)号：US08634235B2

    公开(公告)日：2014-01-21

    申请号：US12823508

    申请日：2010-06-25

    申请人： Hsiang-Lan Lung ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    发明人： Hsiang-Lan Lung ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

    摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

    摘要翻译： 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

    3D polysilicon ROM and method of fabrication thereof
    7.
    发明申请
    3D polysilicon ROM and method of fabrication thereof 有权
    3D多晶硅ROM及其制造方法

    公开(公告)号：US20050124116A1

    公开(公告)日：2005-06-09

    申请号：US10728767

    申请日：2003-12-08

    申请人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

    发明人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

    IPC分类号： H01L21/336 ,  H01L27/06 ,  H01L31/113

    CPC分类号： H01L27/0688

    摘要： A 3D polysilicon read only memory at least including: a silicon substrate, an isolated silicon dioxide (SiO2) layer, a N-Type heavily doped (N+) polysilicon layer, a first oxide layer, a dielectric layer, a P-Type lightly doped (P−) polysilicon layer, at least a neck structure, and a second oxide layer. The isolated SiO2 layer is deposited on the silicon substrate, and the N+ polysilicon layer is deposited on the isolated SiO2 layer. The N+ polysilicon layer is further defined a plurality of parallel, separate word lines (WL), and the first oxide layer is filled in the space between the word lines. The dielectric layer is deposited on the word lines and the first oxide layer. The P-Type lightly doped (P−) polysilicon layer is deposited on the dielectric layer and is further defined a plurality of parallel, separate bit lines (BL). The bit lines overlap the word lines, from a top view, to form a shape approximately as a cross. There are at least a neck structure individually formed between the first polysilicon layer and the second polysilicon layer by isotropy wet etching the dielectric layer, with using dilute hydrofluoric acid (HF) as the example. The second oxide layer is filled in the space between the bit lines and is on the word lines and the first oxide layer.

    摘要翻译： 至少包括硅衬底，隔离二氧化硅（SiO 2）层，N型重掺杂（N +）多晶硅层，第一氧化物层，电介质 层，P型轻掺杂（P）多晶硅层，至少颈部结构和第二氧化物层。 隔离的SiO 2层沉积在硅衬底上，并且N +多晶硅层沉积在隔离的SiO 2层上。 N +多晶硅层进一步限定多个平行的单独的字线（WL），并且第一氧化物层被填充在字线之间的空间中。 介电层沉积在字线和第一氧化物层上。 P型轻掺杂（P）多晶硅层沉积在电介质层上，并进一步限定多个平行的分开的位线（BL）。 位线从顶视图与字线重叠，以形成大致为十字形的形状。 通过使用稀氢氟酸（HF）作为实例，通过各向同性湿蚀刻介电层，至少在第一多晶硅层和第二多晶硅层之间形成颈部结构。 第二氧化物层填充在位线之间的空间中，并且位于字线和第一氧化物层上。

    3D polysilicon ROM and method of fabrication thereof
    8.
    发明授权
    3D polysilicon ROM and method of fabrication thereof 有权
    3D多晶硅ROM及其制造方法

    公开(公告)号：US06952038B2

    公开(公告)日：2005-10-04

    申请号：US10728767

    申请日：2003-12-08

    申请人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

    发明人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

    IPC分类号： H01L21/336 ,  H01L27/06 ,  H01L31/113

    CPC分类号： H01L27/0688

    摘要： A 3D polysilicon ROM including an isolated SiO2 layer on a silicon substrate, and an N+ polysilicon layer on the isolated SiO2 layer. The N+ polysilicon layer is further defined by a plurality of parallel, separate word lines. A first oxide layer fills the space between the word lines. A dielectric layer is deposited on the word lines and the first oxide layer. A P− polysilicon layer is deposited on the dielectric layer and further defines a plurality of parallel, separate bit lines. The bit lines overlap the word lines, from a top view, to form an approximately cross shape. The neck structure may be individually formed between the P− and N+ polysilicon layers by wet etching the dielectric layer with dilute hydrofluoric acid. A second oxide layer fills the space between the bit lines and is on the word lines and the first oxide layer.

    摘要翻译： 在硅衬底上包括隔离的SiO 2层的三维多晶硅ROM和分离的SiO 2层上的N +多晶硅层。 N +多晶硅层进一步由多个平行的单独的字线限定。 第一氧化物层填充字线之间的空间。 介电层沉积在字线和第一氧化物层上。 P-多晶硅层沉积在电介质层上并进一步限定多个平行的分开的位线。 位线从顶视图与字线重叠，以形成大致十字形状。 通过用稀氢氟酸湿式蚀刻介电层，可以在P和N +多晶硅层之间分别形成颈部结构。 第二氧化物层填充位线之间的空间，并且位于字线和第一氧化物层上。

    Method of determining optimal voltages for operating two-side non-volatile memory and the operating methods
    9.
    发明授权
    Method of determining optimal voltages for operating two-side non-volatile memory and the operating methods 有权
    确定操作双侧非易失性存储器的最佳电压的方法和操作方法

    公开(公告)号：US07038928B1

    公开(公告)日：2006-05-02

    申请号：US10991537

    申请日：2004-11-17

    申请人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

    发明人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

    IPC分类号： G11C17/00

    CPC分类号： G11C16/12 ,  G11C16/0475 ,  G11C16/26

    摘要： A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm (=I2(VgO)−I1(VgO)).

    摘要翻译： 描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。 存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是 测量，其中Vg是栅极电压。 绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。 确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。

    METHOD OF DETERMINING OPTIMAL VOLTAGES FOR OPERATING TWO-SIDE NON-VOLATILE MEMORY AND THE OPERATING METHODS
    10.
    发明申请
    METHOD OF DETERMINING OPTIMAL VOLTAGES FOR OPERATING TWO-SIDE NON-VOLATILE MEMORY AND THE OPERATING METHODS 有权
    确定用于操作两侧非易失性存储器的最佳电压的方法和操作方法

    公开(公告)号：US20060104105A1

    公开(公告)日：2006-05-18

    申请号：US10991537

    申请日：2004-11-17

    申请人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

    发明人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung

    IPC分类号： G11C17/00

    CPC分类号： G11C16/12 ,  G11C16/0475 ,  G11C16/26

    摘要： A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm(=I2(VgO)−I1(VgO)).

    摘要翻译： 描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。 存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是 测量，其中Vg是栅极电压。 绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。 确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。