公开(公告)号：US20120161096A1

公开(公告)日：2012-06-28

申请号：US12979461

申请日：2010-12-28

申请人： Fabio Pellizzer ,  Antonino Rigano

发明人： Fabio Pellizzer ,  Antonino Rigano

IPC分类号： H01L27/24 ,  H01L21/02

CPC分类号： H01L27/2463 ,  G11C13/0004 ,  H01L27/0207 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

摘要： A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.

摘要翻译： 描述了具有减少的编程干扰及其操作的相变存储器件。 相变存储器包括具有字线和位线的阵列和耦合到与寻址位线相邻的位线的电压控制元件，以将相邻位线的电压维持在允许的范围内。

公开(公告)号：US07985959B2

公开(公告)日：2011-07-26

申请号：US12218171

申请日：2008-07-11

申请人： Michele Magistretti ,  Fabio Pellizzer ,  Augusto Benvenuti ,  Marcello Mariani

发明人： Michele Magistretti ,  Fabio Pellizzer ,  Augusto Benvenuti ,  Marcello Mariani

IPC分类号： H01L29/02 ,  H01L27/082

CPC分类号： H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A phase change memory may include self-aligned polysilicon vertical bipolar junction transistors used as select devices. The bipolar junction transistors may be formed with double shallow trench isolation. For example, the emitters of each bipolar transistor may be defined by a first set of parallel trenches in one direction and a second set of parallel trenches in the opposite direction. In some embodiments, the formation of parasitic PNP transistors between adjacent emitters may be avoided.

摘要翻译： 相变存储器可以包括用作选择器件的自对准多晶硅垂直双极结型晶体管。 双极结型晶体管可以形成双浅沟槽隔离。 例如，每个双极晶体管的发射极可以由一个方向上的第一组平行沟槽和相反方向上的第二组平行沟槽限定。 在一些实施例中，可以避免在相邻发射器之间形成寄生PNP晶体管。

公开(公告)号：US20110039391A1

公开(公告)日：2011-02-17

申请号：US12912829

申请日：2010-10-27

申请人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

发明人： Agostino Pirovano ,  Augusto Benvenuti ,  Fabio Pellizzer ,  Giorgio Servalli

IPC分类号： H01L21/331

CPC分类号： H01L29/73 ,  H01L27/24

摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.

摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少

公开(公告)号：US07563684B2

公开(公告)日：2009-07-21

申请号：US11264084

申请日：2005-11-01

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

IPC分类号： H01L21/8226

CPC分类号： H01L29/685 ,  H01L27/101 ,  H01L27/24

摘要： A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

摘要翻译： 一种用于制造单元阵列的方法，包括：在第一导电类型的半导体材料的主体中注入第一导电类型的共同导电区域; 在体内在公共导电区域上形成第二导电类型和第一掺杂水平的多个有源区域区域; 在所述主体的顶部上形成具有第一和第二开口的绝缘层; 通过第一导电类型的掺杂剂将有源区域的第一部分注入第一开口，从而在有源区域中形成第一导电类型的第二导电区域; 通过第二导电类型的掺杂剂将有源区域的第二部分注入第二开口，由此形成高于第一掺杂级的第二导电类型和第二掺杂级的控制接触区; 在主体的顶部上形成多个存储部件，每个存储部件具有连接到相应的第二传导区域的端子。

公开(公告)号：US07560782B2

公开(公告)日：2009-07-14

申请号：US11605190

申请日：2006-11-27

申请人： Fabio Pellizzer ,  Paolo Giuseppe Cappelletti

发明人： Fabio Pellizzer ,  Paolo Giuseppe Cappelletti

IPC分类号： H01L29/76

CPC分类号： H01L27/24 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L21/8249 ,  H01L27/0705

摘要： An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

摘要翻译： 集成晶体管器件形成在半导体材料的芯片中，其具有限定容纳垂直型双极晶体管的有源区域的电绝缘区域和彼此相邻的平面型MOSFET。 活动区域容纳收集区域; 与集电极区域相邻的双极基极区域; 在双极基区内的发射极区; 源极区域，布置在距离双极基极区域一定距离处; 漏区; 布置在源极区域和漏极区域之间的沟道区域; 和一个井区。 漏极区域和双极基极区域是连续的，并且形成由双极晶体管和MOSFET共享的公共基极结构。 因此，集成晶体管器件具有高输入阻抗并且能够驱动高电流，同时仅需要小的积分面积。

公开(公告)号：US07439536B2

公开(公告)日：2008-10-21

申请号：US11398858

申请日：2006-04-06

申请人： Fabio Pellizzer ,  Enrico Varesi ,  Agostino Pirovano

发明人： Fabio Pellizzer ,  Enrico Varesi ,  Agostino Pirovano

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： A phase change memory cell includes a phase change region of a phase change material, a heating element of a resistive material, arranged in contact with the phase change region and a memory element formed in said phase change region at a contact area with the heating element. The contact area is in the form of a frame that has a width of sublithographic extent and, preferably, a sublithographic maximum external dimension. The heating element includes a hollow elongated portion which is arranged in contact with the phase change region.

摘要翻译： 相变存储单元包括相变材料的相变区域，与该相变区域接触的电阻材料的加热元件，以及形成在与该加热元件的接触区域的所述相变区域中的存储元件 。 接触区域是具有亚光刻范围宽度的框架形式，最好是亚光刻最大外部尺寸。 加热元件包括与相变区域接触地布置的中空细长部分。

公开(公告)号：US20080203379A1

公开(公告)日：2008-08-28

申请号：US12037766

申请日：2008-02-26

申请人： Michele Magistretti ,  Fabio Pellizzer ,  Augusto Benvenuti

发明人： Michele Magistretti ,  Fabio Pellizzer ,  Augusto Benvenuti

IPC分类号： H01L45/00 ,  H01L27/082 ,  H01L21/8222

CPC分类号： H01L27/1022 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.

摘要翻译： 一种用于制造双极晶体管阵列的方法，其中介电材料的深场绝缘区形成在半导体本体中，从而限定出彼此绝缘的多个有源区，并且在每个有源区中形成多个双极晶体管。 特别地，在每个有源区域中，在半导体本体的表面一定距离处形成第一导电区域; 在第一导电区域上形成控制区域; 并且在每个控制区域中形成至少两个第二导电区域和至少一个控制接触区域。 控制接触区域介于第二导电区域之间，并且至少两个表面场绝缘区域在控制接触区域和第二导电区域之间的每个有效区域中热生长。

公开(公告)号：US20080151612A1

公开(公告)日：2008-06-26

申请号：US11949598

申请日：2007-12-03

申请人： Fabio Pellizzer ,  Agostino Pirovano

发明人： Fabio Pellizzer ,  Agostino Pirovano

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79

摘要： A method and apparatus for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states with resistance levels there between. The method includes using programming pulses to program the phase change memory cell in either the set, reset, or one of the intermediate states. To program in the intermediate states, a programming pulse creates a crystalline percolation path having an average diameter through amorphous phase change material and a second programming pulse modifies the diameter of the crystalline percolation path to program the phase change memory cell to the proper current level.

摘要翻译： 公开了一种用于编程相变存储器单元的方法和装置。 相变存储单元包括具有第一状态的相变材料的存储元件，其中所述相变材料是晶体并且具有最小电阻水平，所述相变材料是非晶态且具有最大电阻的第二状态 电平以及其间具有电阻电平的多个中间状态。 该方法包括使用编程脉冲来对置换，复位或中间状态之一的相变存储器单元进行编程。 为了在中间状态进行编程，编程脉冲产生具有通过非晶相变材料的平均直径的结晶渗透路径，而第二编程脉冲修改晶体渗滤路径的直径以将相变存储器单元编程到适当的电流水平。

公开(公告)号：US07244956B2

公开(公告)日：2007-07-17

申请号：US10824631

申请日：2004-04-14

申请人： Fabio Pellizzer

发明人： Fabio Pellizzer

IPC分类号： H01L47/00 ,  H01L29/02

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/101 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

摘要： A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture.

摘要翻译： 一种相变存储单元的制造方法，包括以下步骤：形成电阻元件; 形成在所述电阻元件上具有孔径的限定结构; 在所述孔中形成相变材料的存储部分，所述电阻元件和所述存储器部分直接电接触并限定亚光刻延伸部的接触面积。 形成存储器部分的步骤还包括用相变材料填充孔，并且从限定结构去除超过孔的相变材料的超过部分。

公开(公告)号：US20070099347A1

公开(公告)日：2007-05-03

申请号：US11551170

申请日：2006-10-19

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC分类号： H01L21/00

CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

摘要： A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

摘要翻译： 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。