公开(公告)号：US06703798B2

公开(公告)日：2004-03-09

申请号：US10372388

申请日：2003-02-25

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： H05B3702

CPC分类号： H05B41/2928 ,  H05B41/392 ,  Y02B20/208

摘要： A discharge lamp lighting device for AC lighting has PT(21), CT1(22), a fluctuation detection circuit (28), and a control circuit (36). PT(21) detects a voltage to be supplied to a HID bulb (5) and CT1(22) detects a current to be supplied to the HID bulb (5). The fluctuation detection circuit (28) generates an output power equivalent value obtained by adding each voltage value corresponding to each detected value by PT(21) and CT1(22), and outputs the fluctuation signal corresponding to the change of the output power equivalent value. The control circuit (36) changes a duty ratio of a control signal to be supplied to the switching transistor (6) according to the fluctuation signal.

摘要翻译： 用于交流照明的放电灯点亮装置具有PT（21），CT1（22），波动检测电路（28）和控制电路（36）。 PT（21）检测要提供给HID灯泡（5）的电压，CT1（22）检测要提供给HID灯泡（5）的电流。 波动检测电路（28）生成通过将与各检测值相对应的各电压值与PT（21）和CT1（22）相加而得到的输出功率等价值，并输出与输出功率等效值的变化对应的波动信号 。 控制电路（36）根据波动信号改变提供给开关晶体管（6）的控制信号的占空比。

公开(公告)号：US06632723B2

公开(公告)日：2003-10-14

申请号：US10132520

申请日：2002-04-26

申请人： Shinichi Watanabe ,  Takashi Ohsawa ,  Kazumasa Sunouchi ,  Yoichi Takegawa ,  Takeshi Kajiyama

发明人： Shinichi Watanabe ,  Takashi Ohsawa ,  Kazumasa Sunouchi ,  Yoichi Takegawa ,  Takeshi Kajiyama

IPC分类号： H01L2176

CPC分类号： H01L21/823481 ,  H01L21/763

摘要： A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.

摘要翻译： 公开了一种半导体器件，其包括半导体衬底，MOS晶体管的漏极和源极区域，形成在MOS晶体管沟槽型元件隔离区域的沟道区域的表面中的栅电极，其中形成绝缘膜 在形成在半导体衬底的表面中的沟槽的表面上，元件隔离区域在沟道宽度方向上从其相对侧夹着沟道区域，以及嵌入在沟槽宽度方向上的背栅电极用导电材料层 被配置为被提供预定电压以在半导体衬底的位于MOS晶体管的沟道区域的区域内的耗尽层或者对半导体衬底区域进行电压控制的元件隔离区域中的至少一个。 PTEXT>

公开(公告)号：US06292424B1

公开(公告)日：2001-09-18

申请号：US09650642

申请日：2000-08-30

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： G11C800

CPC分类号： G11C11/4074 ,  G11C5/147

摘要： A DRAM includes first to third voltage lowering circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first to third voltage lowering circuits are separately provided. The first voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor. The first voltage lowering circuit is an exclusive circuit for creating a first potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a {overscore (RAS)} signal input buffer, {overscore (CAS)} signal input buffer and {overscore (WE)} signal input buffer. The second voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor or source follower type circuit having an N-channel MOS transistor. The second voltage lowering circuit is an exclusive circuit for creating a second potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a VBL generating circuit for generating a bit line precharge potential and a VPL generating circuit for generating a cell plate potential. The third voltage lowering circuit is a source follower type circuit having an N-channel MOS transistor. The third voltage lowering circuit is a circuit for creating a third potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to all of the other internal circuits except the above circuits.

摘要翻译： DRAM包括用于降低从外部供应的电源电压并将降低的电压提供给内部电路的第一至第三降压电路。 分开提供第一至第三降压电路。 第一降压电路是具有P沟道MOS晶体管的反馈型电路。 第一降压电路是用于通过降低从外部供应的电源电压并将如此产生的降低的电源电压提供给（超核（RAS））信号输入缓冲器（超核（CAS））而产生第一电位的专用电路， }信号输入缓冲器和{overscore（WE）}信号输入缓冲器。 第二降压电路是具有具有N沟道MOS晶体管的P沟道MOS晶体管或源极跟随器电路的反馈型电路。 第二降压电路是用于通过降低从外部供给的电源电压并将由此产生的降低的电源电压提供给用于产生位线预充电电位的VBL产生电路并产生VPL产生电路而产生第二电位的专用电路 用于产生细胞板电位。 第三降压电路是具有N沟道MOS晶体管的源极跟随器电路。 第三降压电路是通过降低从外部供给的电源电压来产生第三电位的电路，并将如此产生的降低的电源电压提供给除了上述电路以外的所有其他内部电路。

公开(公告)号：US6122215A

公开(公告)日：2000-09-19

申请号：US365870

申请日：1999-08-03

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  H01L21/822 ,  H01L27/04 ,  G11C8/00

CPC分类号： G11C5/147 ,  G11C11/4074

摘要： A DRAM includes first to third voltage lowering-circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first to third voltage lowering circuits are separately provided. The first voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor. The first voltage lowering circuit is an exclusive circuit for creating a first potential by lowering thus power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a RAM signal input buffer, CAS signal input buffer and WE signal input buffer. The second voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor or source follower type circuit having an N-channel MOS transistor. The second voltage lowering circuit is an exclusive circuit for creating a second potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a V.sub.BL generating circuit for generating a bit line precharge potential and a V.sub.PL generating circuit for generating a cell plate potential. The third voltage lowering circuit is a source follower type circuit having an N-channel MOS transistor. The third voltage lowering circuit is a circuit for creating a third potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to all of the other internal circuits except the above circuits.

摘要翻译： DRAM包括用于降低从外部供应的电源电压的第一至第三降压电路，并将降低的电压提供给内部电路。 分开提供第一至第三降压电路。 第一降压电路是具有P沟道MOS晶体管的反馈型电路。 第一降压电路是用于通过降低从外部供应的电源电压来产生第一电位的专用电路，并将由此产生的降低的电源电压提供给+ E，ovs RAM + EE信号输入缓冲器+ E，ovs CAS + EE信号输入缓冲器和+ E，ovs WE + EE信号输入缓冲器。 第二降压电路是具有具有N沟道MOS晶体管的P沟道MOS晶体管或源极跟随器电路的反馈型电路。 第二降压电路是用于通过降低从外部供给的电源电压并将由此产生的降低的电源电压提供给用于产生位线预充电电位的VBL产生电路并产生VPL产生电路而产生第二电位的专用电路 用于产生细胞板电位。 第三降压电路是具有N沟道MOS晶体管的源极跟随器电路。 第三降压电路是通过降低从外部供给的电源电压来产生第三电位的电路，并将如此产生的降低的电源电压提供给除了上述电路以外的所有其他内部电路。

公开(公告)号：US5854768A

公开(公告)日：1998-12-29

申请号：US4384

申请日：1998-01-08

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  H01L21/822 ,  H01L27/04 ,  H01L21/00

CPC分类号： G11C5/147 ,  G11C11/4074

摘要： A DRAM includes first to third voltage lowering circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first to third voltage lowering circuits are separately provided. The first voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor. The first voltage lowering circuit is an exclusive circuit for creating a first potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a RAS signal input buffer, CAS signal input buffer and WE signal input buffer. The second voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor or source follower type circuit having an N-channel MOS transistor. The second voltage lowering circuit is an exclusive circuit for creating a second potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a V.sub.BL generating circuit for generating a bit line precharge potential and a V.sub.PL generating circuit for generating a cell plate potential. The third voltage lowering circuit is a source follower type circuit having an N-channel MOS transistor.

摘要翻译： DRAM包括用于降低从外部供应的电源电压并将降低的电压提供给内部电路的第一至第三降压电路。 分开提供第一至第三降压电路。 第一降压电路是具有P沟道MOS晶体管的反馈型电路。 第一降压电路是用于通过降低从外部供应的电源电压并将由此产生的降低的电源电压提供给+ E，ovs RAS + EE信号输入缓冲器+ E，ovs来产生第一电位的专用电路 CAS + EE信号输入缓冲器和+ E，ovs WE + EE信号输入缓冲器。 第二降压电路是具有具有N沟道MOS晶体管的P沟道MOS晶体管或源极跟随器电路的反馈型电路。 第二降压电路是用于通过降低从外部供给的电源电压并将由此产生的降低的电源电压提供给用于产生位线预充电电位的VBL产生电路并产生VPL产生电路而产生第二电位的专用电路 用于产生细胞板电位。 第三降压电路是具有N沟道MOS晶体管的源极跟随器电路。

公开(公告)号：US5592421A

公开(公告)日：1997-01-07

申请号：US393077

申请日：1995-02-23

申请人： Tetsuya Kaneko ,  Takashi Ohsawa

发明人： Tetsuya Kaneko ,  Takashi Ohsawa

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C8/08

摘要： A semiconductor integrated circuit device is provided that can restrict changes in the internal power source potential when an externally applied power source potential changes. The semiconductor integrated circuit device comprises an integrated circuit section, a voltage regulator for limiting an externally applied potential which causes changes in potential levels to a certain potential level to obtain a regulated potential, and a boost circuit driven by the regulated potential as a power source, for boosting the regulated potential to a boosted potential used as a operating power source for the integrated circuit section. The boost circuit is driven by the regulated potential limited to a certain potential level. Even when the level of the potential VCC changes, operation of the boost circuit does not substantially change. Due to the structure in which the boosted potential is generated from the regulated potential, the constant potential range of the boosted potential is enlarged so that operating margins of the device are enlarged.

摘要翻译： 提供了一种半导体集成电路器件，其可以在外部施加的电源电位变化时限制内部电源电位的变化。 半导体集成电路器件包括集成电路部分，用于限制外部施加的电位的电压调节器，其将电位电平的变化导致一定的电位以获得调节电位，以及由调节电位驱动的升压电路作为电源 ，用于将调节电位升高到用作集成电路部分的工作电源的升压电位。 升压电路由限制在一定电位电平的调节电位驱动。 即使当电位VCC的电平变化时，升压电路的操作也实质上不会改变。 由于从调节电位产生升压电位的结构，增大了电位的恒定电位范围，从而扩大了器件的工作裕度。

公开(公告)号：US5587958A

公开(公告)日：1996-12-24

申请号：US363825

申请日：1994-12-27

申请人： Tetsuya Kaneko ,  Takashi Ohsawa

发明人： Tetsuya Kaneko ,  Takashi Ohsawa

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C11/4085 ,  G11C5/145

摘要： A semiconductor integrated circuit device includes a boost potential generation circuit, word line drive system circuit, refresh cycle select circuit, word line system boost potential generation circuit and boost potential generation system control circuit. The boost potential generation circuit steadily generates a higher boost potential than an externally applied voltage. The word line drive system circuit delivers the boost potential, as a power supply, from the boost potential generation circuit so as to drive the corresponding word line. The word line system boost potential control circuit sets at a substantially constant level a boost potential output from the boost potential generation circuit. The boost potential generation system control circuit receives a designation signal from the refresh cycle select circuit so as to designate a refresh cycle and supplies a control signal, which is generated based on the designation signal, to the boost potential generation circuit, whereby, when more word lines are driven at a time by the word line system drive circuit, a current supply capability of the boost potential generation circuit is increased and, when less word lines are driven at a time, the current supply capability of the boost potential generation circuit is decreased.

摘要翻译： 半导体集成电路器件包括升压电位产生电路，字线驱动系统电路，刷新周期选择电路，字线系统升压电位产生电路和升压电位发生系统控制电路。 升压电位发生电路稳定地产生比外部施加的电压更高的升压电位。 字线驱动系统电路从升压电位产生电路提供升压电位作为电源，以驱动相应的字线。 字线系统升压电位控制电路将从升压电位产生电路输出的升压电位设定为基本恒定的电平。 升压电位生成系统控制电路从刷新周期选择电路接收指定信号，以指定刷新周期，并将基于指定信号生成的控制信号提供给升压电位产生电路，从而当更多 字线由字线系驱动电路一次驱动，升压电位产生电路的电流供给能力增加，当一次驱动较少的字线时，升压电位产生电路的电流供给能力为 减少。

公开(公告)号：US5323345A

公开(公告)日：1994-06-21

申请号：US676073

申请日：1991-03-27

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/407 ,  H03F3/45

CPC分类号： G11C11/4096 ,  G11C11/4091

摘要： A dynamic type semiconductor memory device is disclosed which includes a plurality of memory cells, plural pairs of bit lines for supplying data to the plurality of memory cells, a first sense amplifier arranged for each of the plural pairs of bit lines, for amplifying a bit line signal, a pair of data input/output lines consisting of first and second data input/output lines, for extracting data from the plural pairs of bit lines, a second sense amplifier arranged for each of the plural pairs of bit lines and consisting of first and second driver MOS transistors for extracting charges from the data input/output lines in a data reading operation, and for amplifying a data input/output line signal, first and second column selecting transistors which are inserted between the pair of data input/output lines and the second sense amplifier and gates of which are connected to a column selecting line, and first and second write transistors, the first and second write transistors being turned on in a data writing operation.

摘要翻译： 公开了一种动态型半导体存储器件，其包括多个存储器单元，用于向多个存储器单元提供数据的多对位线，为多对位线中的每一对布置的第一读出放大器，用于放大位 线信号，由第一和第二数据输入/输出线组成的一对数据输入/输出线，用于从多对位线提取数据;第二读出放大器，被布置用于多对位线中的每一对，并由 第一和第二驱动器MOS晶体管，用于在数据读取操作中从数据输入/输出线提取电荷，并且用于放大数据输入/输出线信号，第一和第二列选择晶体管插入在该对数据输入/输出 线，并且其第二读出放大器和栅极连接到列选择线，以及第一和第二写晶体管，第一和第二写晶体管转为o n在数据写入操作中。

公开(公告)号：US5166558A

公开(公告)日：1992-11-24

申请号：US675952

申请日：1991-03-27

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： G11C11/409 ,  H03K19/0185

CPC分类号： H03K19/018521 ,  H03K19/018514

摘要： According to this invention, there is disclosed an output circuit including a MOS transistor having two current paths inserted between a power source voltage and an output terminal, a MOS transistor having two current paths inserted between a power source voltage and the output terminal, a differential amplifier for comparing a reference voltage with an voltage at the output terminal, a differential amplifier for comparing a reference voltage lower than the reference voltage with the voltage at the output terminal, an input terminal for applying an input voltage, a logic gate for receiving an output from the differential amplifier and the input voltage, the logic gate having an output terminal connected to a gate of the MOS transistor, and a logic gate for receiving an output from the differential amplifier and the input voltage, the logic gate having an output terminal connected to a gate of the MOS transistor.

公开(公告)号：US5034661A

公开(公告)日：1991-07-23

申请号：US453828

申请日：1989-12-20

申请人： Takehiko Sakurai ,  Takeo Saikatsu ,  Yoshinori Anazi ,  Hiroyoshi Yamazaki ,  Katsuo Murakami ,  Seishiro Mitsuhashi ,  Takashi Ohsawa

发明人： Takehiko Sakurai ,  Takeo Saikatsu ,  Yoshinori Anazi ,  Hiroyoshi Yamazaki ,  Katsuo Murakami ,  Seishiro Mitsuhashi ,  Takashi Ohsawa

IPC分类号： G03G15/04 ,  H01J61/76 ,  H05B41/282

CPC分类号： G03G15/04036 ,  H01J61/76 ,  H05B41/2824 ,  H01J61/35 ,  H01J61/56 ,  Y10S315/05

摘要： The invention provides a rare gas discharge fluorescent lamp device which is long in life and high in brightness and efficiency. The lamp device comprises a rare gas discharge fluorescent lamp including a bulb having rare gas such as xenon, argon or krypton gas enclosed therein, a fluorescent layer formed on an inner face of the bulb, a reflecting film formed on an inner face of the fluorescent layer, and a pair of electrodes located at the opposite ends of the bulb. The lamp device further comprises a power source for applying a voltage across the electrodes, and pulse voltage forming means connected between the electrodes and the power source for forming a dc pulse voltage from a voltage supplied from the power source. The dc pulse voltage thus formed is applied across the electrodes to cause the lamp to be lit. The pulse frequency of the pulse voltage and the enclosed gas pressure are determined depending upon the rare gas employed, and particularly where dc rectangular pulses are used, the duty ratio is also determined depending upon the rare gas employed.