公开(公告)号：US20150311337A1

公开(公告)日：2015-10-29

申请号：US14792742

申请日：2015-07-07

申请人： GLOBALFOUNDRIES Inc.

发明人： Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/785 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

摘要： Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.

摘要翻译： 本文公开了在FinFET和其它半导体器件上形成隔离结构的各种方法，以及具有这种隔离结构的所得器件。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于FinFET器件的鳍片，在沟槽中形成绝缘材料层，其中绝缘材料层覆盖下部 翅片的一部分而不是翅片的上部，在翅片的上部形成保护材料，并且在氧化环境中进行加热处理，以在翅片的被覆盖的下部形成热氧化物区域。

公开(公告)号：US20150279999A1

公开(公告)日：2015-10-01

申请号：US14732938

申请日：2015-06-08

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7856 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.

摘要翻译： 所公开的一种方法包括：在牺牲材料层的堆叠中形成牺牲栅极结构沟槽，在沟槽内形成牺牲栅极结构，执行至少一个处理操作以移除堆叠的牺牲材料层的至少一部分，从而暴露侧壁 形成邻近牺牲栅极结构的暴露的侧壁的侧壁间隔物，去除牺牲栅极结构，以在间隔物之间​​限定替换栅极腔，在置换栅腔中形成替代栅极结构，并形成 位于置换门腔内的替换栅极结构上方的栅极盖。

公开(公告)号：US09117908B2

公开(公告)日：2015-08-25

申请号：US14107279

申请日：2013-12-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei

IPC分类号： H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L29/7856 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.

摘要翻译： 所公开的一种方法包括：在牺牲材料层的堆叠中形成牺牲栅极结构沟槽，在沟槽内形成牺牲栅极结构，执行至少一个处理操作以移除堆叠的牺牲材料层的至少部分，从而暴露侧壁 形成邻近牺牲栅极结构的暴露的侧壁的侧壁间隔物，去除牺牲栅极结构，以在间隔物之间​​限定替换栅极腔，在置换栅腔中形成替代栅极结构，并形成 位于置换门腔内的替换栅极结构上方的栅极盖。

公开(公告)号：US20150206844A1

公开(公告)日：2015-07-23

申请号：US14159944

申请日：2014-01-21

申请人： International Business Machines Corporation ,  Globalfoundries, Inc.

发明人： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06

CPC分类号： H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

摘要翻译： 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

公开(公告)号：US09070742B2

公开(公告)日：2015-06-30

申请号：US13745547

申请日：2013-01-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Xiuyu Cai

IPC分类号： H01L21/70 ,  H01L27/088 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： Methods for fabricating FinFET integrated circuits with uniform fin height and ICs fabricated from such methods are provided. A method includes etching a substrate using an etch mask to form fins. A first oxide is formed between the fins. A first etch stop is deposited on the first oxide. A second oxide is formed on the first etch stop. A second etch stop is deposited on the second oxide. A third oxide is deposited overlying the second etch stop. An STI extends from at least a surface of the substrate to at least a surface of the second etch stop overlying the fins to form a first active region and a second active region. The first etch stop overlying the fins is removed. The third oxide is removed to expose the second etch stop. A gate stack is formed overlying a portion of each of the fins.

摘要翻译： 提供了制造具有均匀翅片高度的FinFET集成电路的方法和由这些方法制造的IC。 一种方法包括使用蚀刻掩模蚀刻衬底以形成鳍片。 在翅片之间形成第一氧化物。 第一蚀刻停止层沉积在第一氧化物上。 在第一蚀刻停止件上形成第二氧化物。 第二蚀刻停止层沉积在第二氧化物上。 沉积在第二蚀刻停止层上的第三氧化物。 STI从衬底的至少一个表面延伸到覆盖鳍片的第二蚀刻停止件的至少一个表面，以形成第一有源区域和第二有源区域。 去除覆盖翅片的第一个蚀刻停止。 去除第三氧化物以暴露第二蚀刻停止。 形成了覆盖每个散热片的一部分的栅极叠层。

公开(公告)号：US09064890B1

公开(公告)日：2015-06-23

申请号：US14223545

申请日：2014-03-24

申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

摘要： One method disclosed includes, among other things, forming an initial fin, covering a top surface and a portion of the sidewalls of the initial fin structure with etch stop material, forming a sacrificial gate structure above and around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the initial fin structure so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure, and substantially filling the channel cavity with an insulating material.

摘要翻译： 公开的一种方法包括形成初始翅片，用蚀刻停止材料覆盖初始翅片结构的顶表面和一部分侧壁，在初始翅片结构的上方和周围形成牺牲栅结构，形成侧壁 邻近牺牲栅极结构的间隔件，执行至少一个处理操作以去除牺牲栅极结构，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺以去除初始鳍结构的一部分，从而 从而限定最终翅片结构和位于最终翅片结构下方的通道腔，并且用绝缘材料基本上填充通道腔。

公开(公告)号：US09029920B2

公开(公告)日：2015-05-12

申请号：US13909328

申请日：2013-06-04

申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

发明人： Ruilong Xie ,  Xiuyu Cai ,  Vimal Kamineni ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section.

摘要翻译： 提供具有减小的栅极和/或接触电阻的半导体结构和制造方法。 该方法包括：提供半导体器件，其包括形成半导体器件的晶体管，其中晶体管形成包括：形成用于晶体管的T形栅极，T形栅极呈垂直截面为T形; 并且在晶体管的有源区域形成倒T形的接触，所述倒T形接触件包括在横截面上具有倒T形的导电结构。

公开(公告)号：US20150108573A1

公开(公告)日：2015-04-23

申请号：US14060874

申请日：2013-10-23

申请人： GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

发明人： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

摘要： A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

摘要翻译： 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

公开(公告)号：US20140327088A1

公开(公告)日：2014-11-06

申请号：US14333135

申请日：2014-07-16

申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/785

摘要： One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

摘要翻译： 本文公开的一种方法包括在限定翅片的多个沟槽中形成共形衬垫层，在衬垫层上方形成绝缘材料层，暴露衬里层的部分，去除衬里层的部分，从而导致 大体呈U形的衬垫，位于每个沟槽的底部，对绝缘材料层进行至少一个第三蚀刻工艺，其中绝缘材料层的至少一部分位于U形的空腔内 衬垫层，并且在翅片周围形成栅极结构。 本文公开的FinFET器件包括限定翅片的多个沟槽，局部隔离，其包括大致U形的衬垫，其部分地限定腔体中定位的空腔和绝缘材料层，以及定位的门结构 围绕翅膀

公开(公告)号：US20140315371A1

公开(公告)日：2014-10-23

申请号：US13864420

申请日：2013-04-17

申请人： GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L29/66 ,  H01L21/762

CPC分类号： H01L21/823821 ,  H01L21/76229 ,  H01L21/76232

摘要： One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that covers a portion of the substrate positioned between the fins while exposing portions of the substrate positioned laterally outside of the patterned liner layer, and performing at least one etching process on the exposed portions of the substrate through the patterned liner layer to define an isolation trench in the substrate, wherein the isolation trench has a depth that is greater than a depth of the fin-formation trenches.

摘要翻译： 本文公开的一种方法包括在半导体衬底中形成限定多个间隔开的翅片的多个翅片形成沟槽，形成图案化的衬里层，该衬底层覆盖位于翅片之间的衬底的一部分，同时使位于衬底 在图案化的衬里层的横向外侧，并且通过图案化的衬里层对衬底的暴露部分执行至少一个蚀刻工艺，以在衬底中限定隔离沟槽，其中隔离沟槽的深度大于 鳍形沟渠。