摘要:
A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
摘要:
Forming a semiconductor structure includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps on sides of a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity. The first and second low-k spacer portions are etched. A poly pull process is performed on the remaining portions of the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
摘要:
Semiconductor devices and methods for making the same includes conformally forming a first spacer on a plurality of fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The plurality of fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.
摘要:
A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.
摘要:
A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.
摘要:
One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.
摘要:
One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.
摘要:
A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.
摘要:
One illustrative embodiment involves forming a plurality of trenches in a substrate so as to define a fin, forming a first oxidation-blocking layer of insulating material in the trenches so as to cover a portion, but not all, of the sidewalls of the lower portion of the fin, forming a second layer of insulating material above the first oxidation-blocking layer of insulating material, and performing a thermal anneal process to convert part, but not all, of the lower portion of the fin positioned above the first oxidation-blocking layer of insulating material into an oxide fin isolation region positioned under the fin.
摘要:
One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.