公开(公告)号：US20070119229A1

公开(公告)日：2007-05-31

申请号：US11599600

申请日：2006-11-14

Applicant: Helmut Fischer

Inventor： Helmut Fischer

IPC: G01B21/08 ,  G01B7/06

CPC classification number: G01B7/105

Abstract: The invention relates to a calibration standard, especially for the calibration of devices for the non-destructive measurement of the thickness of thin layers with a carrier plate (16) of a basic material and a standard (17) applied on the carrier plate (16), said standard having the thickness of the layer at which the device is to be calibrated, wherein that a holding device (22) arranged on the basic body (12) of the calibration standard (11) receives at least the standard (17) to the basic body (12) such that upon setting a measuring probe of the device for the non-destructive measurement of thin layers onto the standard (17), its position will be changeable by at least one degree of freedom.

Abstract translation: 本发明涉及一种校准标准，特别是用于校准具有基材的载体板（16）和施加在载体板（16）上的标准物（17）的薄层厚度的非破坏性测量的装置 ），所述标准具有要在其上校准装置的层的厚度，其中布置在校准标准（11）的基体（12）上的保持装置（22）至少接收标准（17） 到基体（12），使得当将用于薄层的非破坏性测量的装置的测量探针设置到标准（17）上时，其位置将可以至少一个自由度改变。

公开(公告)号：US20070017112A1

公开(公告)日：2007-01-25

申请号：US11490382

申请日：2006-07-20

Applicant: Helmut Fischer

Inventor： Helmut Fischer

IPC: G01B3/22

CPC classification number: G01B7/105 ,  G01B5/0004

Abstract: A measurement stand for holding a measuring device (26), in particular a measuring arrangement (26) for measuring the thickness of thin layers, said measurement stand comprising a housing (18) in which a cam follower (23) is guided such that it can be moved up and down and the measuring device (26) is arranged at that end of said housing (18) that faces the measuring object (14), wherein a drive unit (29) with an electric drive (28) drives the lifting movement of the cam follower (23), wherein said drive unit (29) initiates in the down movement at least one first movement phase with a rapid motion and at least one further movement phase of the cam follower (23) with a creep motion until the measuring device (26) touches down on the measuring object (14).

Abstract translation: 用于保持测量装置（26）的测量台，特别是用于测量薄层厚度的测量装置（26），所述测量支架包括壳体（18），凸轮从动件（23）被引导到所述壳体 可以上下移动，并且测量装置（26）布置在所述壳体（18）的面向测量对象（14）的端部处，其中具有电驱动器（28）的驱动单元（29）驱动提升 凸轮从动件（23）的运动，其中所述驱动单元（29）以向下运动启动具有快速运动的至少一个第一运动相位和凸轮从动件（23）的至少一个进一步运动相位，其具有蠕变运动，直到 测量装置（26）在测量对象（14）上接触。

公开(公告)号：US20060232897A1

公开(公告)日：2006-10-19

申请号：US11389540

申请日：2006-03-27

Applicant: Helmut Fischer ,  Jurgen Lindolf ,  Michael Sommer

Inventor： Helmut Fischer ,  Jurgen Lindolf ,  Michael Sommer

IPC: H02H9/00

CPC classification number: H01L27/0266

Abstract: An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

Abstract translation: 具有静电放电保护的集成电路包括具有源极端子，漏极端子和栅极端子的第一晶体管以及具有源极端子，漏极端子和栅极端子的第二晶体管。 第一和第二晶体管中的每一个的栅极端子连接到漏极端子。 第一晶体管与第二晶体管串联连接，第一晶体管的漏极和源极之一连接到第二晶体管的漏极和源极端之一。 由晶体管形成的串联电路连接到集成电路的输入端子，或连接到施加集成电路的基准电位的电源端子和端子。 晶体管的串联电路由晶体管的数量和晶体管的沟道长度和沟道宽度比的设置来确定。

公开(公告)号：US20060158954A1

公开(公告)日：2006-07-20

申请号：US11319754

申请日：2005-12-29

Applicant: Martin Brox ,  Helmut Fischer

Inventor： Martin Brox ,  Helmut Fischer

IPC: G11C8/00

CPC classification number: G11C11/4076 ,  G11C7/1045 ,  G11C7/22

Abstract: The invention relates to a semiconductor memory device, a system with a semiconductor memory device, and a method for operating a semiconductor memory device, comprising the steps of reading out a data value, in particular a CAS latency time data value (CL) stored in a memory; activating or deactivating a device provided on said semiconductor memory device in support of a high speed operation, as a function of the data value (CL) stored.

Abstract translation: 本发明涉及半导体存储器件，具有半导体存储器件的系统和用于操作半导体存储器件的方法，包括以下步骤：读出数据值，特别是存储在存储器中的CAS等待时间数据值（CL） 记忆 作为存储的数据值（CL）的函数，激活或去激活设置在所述半导体存储器件上的设备以支持高速操作。

公开(公告)号：US20060056241A1

公开(公告)日：2006-03-16

申请号：US11225864

申请日：2005-09-13

Applicant: Juergen Auge ,  Helmut Fischer ,  Manfred Proell ,  Stephan Schroeder

Inventor： Juergen Auge ,  Helmut Fischer ,  Manfred Proell ,  Stephan Schroeder

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C29/50 ,  G11C2029/1204

Abstract: An apparatus for aging a chip, comprising a first bit line connected to a first memory cell; a second bit line connected to a second memory cell; an access circuit for accessing the first memory cell via the first bit line and for accessing the second memory cell via the second bit line; a first controller for selectively connecting/disconnecting the first bit line to the access circuit and from the access circuit, respectively; a second controller for selectively connecting/disconnecting the second bit line to the access circuit and from the access circuit, respectively; a normal operating mode controller for controlling the first and second controller, wherein the normal operating mode controller is formed such to select the first controller in a normal operating mode for accessing the first memory cell, and to connect the access circuit to the first bit line, while the second controller is controlled to disconnect the access circuit from the second bit line; wherein the apparatus comprises: an aging mode controller for controlling the first and second controller, wherein the aging mode controller is formed to control the first controller and the second controller in an aging mode such that the access circuit is connected to the first and second bit lines for a predetermined time period.

Abstract translation: 一种用于老化芯片的装置，包括连接到第一存储器单元的第一位线; 连接到第二存储器单元的第二位线; 访问电路，用于经由所述第一位线访问所述第一存储器单元，以及经由所述第二位线访问所述第二存储器单元; 第一控制器，用于分别选择性地将第一位线连接到接入电路和接入电路; 第二控制器，用于分别选择性地将第二位线连接到接入电路和接入电路; 用于控制第一和第二控制器的正常操作模式控制器，其中形成正常操作模式控制器以便以正常操作模式选择第一控制器以访问第一存储器单元，并将访问电路连接到第一位线 同时控制第二控制器以将访问电路与第二位线断开; 其特征在于，所述装置包括：老化模式控制器，用于控制所述第一和第二控制器，其中所述老化模式控制器被形成为以老化模式控制所述第一控制器和所述第二控制器，使得所述存取电路连接到所述第一和第二位 线条预定时间段。

公开(公告)号：US06986088B2

公开(公告)日：2006-01-10

申请号：US10245622

申请日：2002-09-17

Applicant: Helmut Fischer ,  Johann Pfeiffer ,  Rainer Florian Schnabel

Inventor： Helmut Fischer ,  Johann Pfeiffer ,  Rainer Florian Schnabel

IPC: G01R31/28

CPC classification number: G11C29/12005 ,  G11C29/12

Abstract: The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.

公开(公告)号：US06937537B2

公开(公告)日：2005-08-30

申请号：US10462419

申请日：2003-06-16

Applicant: Johann Pfeiffer ,  Helmut Fischer

Inventor： Johann Pfeiffer ,  Helmut Fischer

IPC: G11C11/408 ,  G11C8/00

CPC classification number: G11C11/4085 ,  G11C11/4087

Abstract: A semiconductor memory includes: at least two memory banks that each have a memory cell matrix, an address decoding unit which includes a bank address decoding unit, a row address decoding unit and a column address decoding unit. At least one demultiplexer is connected upstream of the address buffer memories provided in the row address decoding unit and/or in the column address decoding unit. This demultiplexer is connected to the bank address decoder in order, on the basis of the decoded bank address, to activate the corresponding address buffer memory.

Abstract translation: 半导体存储器包括：至少两个存储单元，每个存储单元具有存储单元矩阵，地址解码单元包括存储体地址解码单元，行地址解码单元和列地址解码单元。 至少一个解复用器连接在行地址解码单元和/或列地址解码单元中提供的地址缓冲存储器的上游。 该解复用器按照解码的存储体地址依次连接到存储体地址解码器，以激活对应的地址缓冲存储器。

公开(公告)号：US06822923B2

公开(公告)日：2004-11-23

申请号：US10425280

申请日：2003-04-29

Applicant: Johann Pfeiffer ,  Helmut Fischer

Inventor： Johann Pfeiffer ,  Helmut Fischer

IPC: G11C800

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2281

Abstract: A RAM memory circuit and method for controlling the same includes memory cells disposed in a matrix of rows and columns each addressed for writing in/reading out a datum by activation of a word line assigned to a relevant row and connection of a sense amplifier assigned to a relevant column to a data path. A control device can be set by an immediate-write command, commanding the write operation, to initiate connection of the sense amplifiers selected by the column addresses provided to the data path at an instant ta+Tw, where ta is the instant of activation of the word line selected by a row address provided and Tw is less than a charging time Tc specific to the memory circuit and is necessary, starting from a word line activation, to transfer the datum stored in a memory cell of the relevant row to the respectively selected sense amplifier and amplify it there.

公开(公告)号：US06771527B2

公开(公告)日：2004-08-03

申请号：US10650818

申请日：2003-08-28

Applicant: Helmut Fischer ,  Athanasia Chrysostomides ,  Kazimierz Szczypinski

Inventor： Helmut Fischer ,  Athanasia Chrysostomides ,  Kazimierz Szczypinski

IPC: G11C506

CPC classification number: G11C11/4097 ,  H01L27/10897

Abstract: An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.

Abstract translation: 集成DRAM存储器组件具有读出放大器，其分别在集成部件的框架内由从单元阵列规则排列的多个晶体管结构以及具有用于位线信号放大的放大晶体管的信号互连结构形成。 放大晶体管具有相同的设计，并且它们在相邻的晶体管行中成对地相对置。 与晶体管行相关联并与其并行延伸的信号互连提供致动信号。 用于致动信号的信号互连具有与放大晶体管相同的布置对称性，这意味着相邻晶体管行中的放大晶体管处于相同的信号互连接近。

公开(公告)号：US06751135B2

公开(公告)日：2004-06-15

申请号：US10310930

申请日：2002-12-05

Applicant: Helmut Fischer ,  Michael Sommer

Inventor： Helmut Fischer ,  Michael Sommer

IPC: G11C800

CPC classification number: G11C11/4085

Abstract: A dynamic semiconductor memory has memory cells disposed in a cell field. The memory cells are connected to master word lines by way of a word line driver for driving the memory cells. As a rule, all the master word lines that are located in the segmented cell field are inactive, with at most one master word line being active. The master word lines are switched to an active low state, and a portion of the master word lines in a region of the cell field are inverted by a control device located at the beginning of the cell field. The deactivated master word lines in the cell field are at a ground potential, which, in view of the large number of existing master word lines, advantageously substantially reduces the leakage current that must be applied by the generators.

Abstract translation: 动态半导体存储器具有设置在单元区域中的存储单元。 存储单元通过用于驱动存储器单元的字线驱动器连接到主字线。 通常，位于分段单元格字段中的所有主字线都是不活动的，最多只有一个主字线处于活动状态。 主字线切换到活动低电平状态，单元区域的一部分主字线由位于电池区开始处的控制装置反相。 单元区域中的去激活的主字线处于接地电位，鉴于大量现有主字线，有利地大大减少了发生器必须施加的漏电流。