公开(公告)号：US20080315296A1

公开(公告)日：2008-12-25

申请号：US12142289

申请日：2008-06-19

申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

公开(公告)号：US08294191B2

公开(公告)日：2012-10-23

申请号：US12943349

申请日：2010-11-10

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。

公开(公告)号：US20120043599A1

公开(公告)日：2012-02-23

申请号：US12943349

申请日：2010-11-10

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。

公开(公告)号：US07755134B2

公开(公告)日：2010-07-13

申请号：US11765881

申请日：2007-06-20

申请人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

发明人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

IPC分类号： H01L27/115

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

摘要翻译： 非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

公开(公告)号：US20060189070A1

公开(公告)日：2006-08-24

申请号：US11117337

申请日：2005-04-29

申请人： Masaru Kidoh ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Hitomi Yasutake

发明人： Masaru Kidoh ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Hitomi Yasutake

IPC分类号： H01L21/8242

CPC分类号： H01L27/10841 ,  H01L27/10867 ,  H01L27/10882

摘要： A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first to third side surfaces in the upper portion of the element region, a gate electrode having first and second bottom surfaces, a first diffusion layer formed along the upper surface of the element region, a second diffusion layer formed along the first side surface in the middle portion of the element region, a channel region having first to third regions formed along the first to third side surfaces in the upper portion of the element region, a capacitor formed in the trench, and a bit line electrically connected to the first diffusion layer.

公开(公告)号：US08410538B2

公开(公告)日：2013-04-02

申请号：US12834390

申请日：2010-07-12

申请人： Megumi Ishiduki ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

发明人： Megumi Ishiduki ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L29/66

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a memory film, and a SiGe film. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the substrate. The memory film includes a charge storage film. The memory film is provided on a sidewall of a memory hole punched through the stacked body. The SiGe film is provided inside the memory film in the memory hole.

摘要翻译： 根据一个实施例，半导体存储器件包括衬底，层叠体，存储膜和SiGe膜。 层叠体包括交替层叠在基板的上方的多个导电层和多个绝缘层。 记忆膜包括电荷存储膜。 记忆膜设置在穿过堆叠体的冲击的存储孔的侧壁上。 SiGe膜被提供在存储器孔内的记忆膜内部。

公开(公告)号：US20110227140A1

公开(公告)日：2011-09-22

申请号：US12834390

申请日：2010-07-12

申请人： Megumi ISHIDUKI ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

发明人： Megumi ISHIDUKI ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a memory film, and a SiGe film. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the substrate. The memory film includes a charge storage film. The memory film is provided on a sidewall of a memory hole punched through the stacked body. The SiGe film is provided inside the memory film in the memory hole.

摘要翻译： 根据一个实施例，半导体存储器件包括衬底，层叠体，存储膜和SiGe膜。 层叠体包括交替层叠在基板的上方的多个导电层和多个绝缘层。 记忆膜包括电荷存储膜。 记忆膜设置在穿过堆叠体的冲击的存储孔的侧壁上。 SiGe膜被提供在存储器孔内的记忆膜内部。

公开(公告)号：US07812396B2

公开(公告)日：2010-10-12

申请号：US11688449

申请日：2007-03-20

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

IPC分类号： H01L23/62

CPC分类号： H01L27/0605 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/12

摘要： A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

摘要翻译： 一种具有第一半导体区域和第二半导体区域的半导体器件，所述第二半导体区域包括形成在形成于半导体衬底上的绝缘层上的杂质，形成在所述第一半导体区域和所述第二半导体区域之间的绝缘体，形成在所述第一半导体 区域和形成在第二半导体区域上的第二杂质扩散控制膜，形成在第一杂质扩散控制膜和第二杂质扩散膜上的沟道层，以与第一半导体区域和第二半导体区域的方向成直角交叉 扩展了形成在沟道层上的栅极绝缘膜和形成在栅极绝缘层上的栅电极。

公开(公告)号：US07459741B2

公开(公告)日：2008-12-02

申请号：US11390255

申请日：2006-03-28

申请人： Masaru Kidoh ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito

发明人： Masaru Kidoh ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito

IPC分类号： H01L29/34

CPC分类号： H01L29/945 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10841 ,  H01L29/7841

摘要： A semiconductor memory device excellent in data holding characteristics even when a cell area is reduced is disclosed. According to one aspect of the present invention, a semiconductor memory device comprises a transistor including a source, a drain and a channel region disposed in a semiconductor substrate, and including a gate electrode disposed through a gate insulator on a surface of the semiconductor substrate of the channel region, a capacitor connected to the channel region, a first wiring line electrically connected to the gate electrode, and a second wiring line electrically connected to the drain.

摘要翻译： 公开了即使在小区面积减小的情况下，数据保持特性优异的半导体存储装置。 根据本发明的一个方面，一种半导体存储器件包括晶体管，其包括源极，漏极和设置在半导体衬底中的沟道区，并且包括通过栅极绝缘体设置在栅极绝缘体的半导体衬底的表面上的栅电极 沟道区，连接到沟道区的电容器，与栅电极电连接的第一布线和与漏极电连接的第二布线。

公开(公告)号：US07977748B2

公开(公告)日：2011-07-12

申请号：US12850783

申请日：2010-08-05

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

IPC分类号： H01L27/12

CPC分类号： H01L27/0605 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/12

摘要： A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

摘要翻译： 一种具有第一半导体区域和第二半导体区域的半导体器件，所述第二半导体区域包括形成在形成于半导体衬底上的绝缘层上的杂质，形成在所述第一半导体区域和所述第二半导体区域之间的绝缘体，形成在所述第一半导体 区域和形成在第二半导体区域上的第二杂质扩散控制膜，形成在第一杂质扩散控制膜和第二杂质扩散膜上的沟道层，以与第一半导体区域和第二半导体区域的方向成直角交叉 扩展了形成在沟道层上的栅极绝缘膜和形成在栅极绝缘层上的栅电极。