公开(公告)号：US06243311B1

公开(公告)日：2001-06-05

申请号：US09507170

申请日：2000-02-18

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G11C700

CPC分类号： H01L27/10891 ,  G11C7/18 ,  G11C11/4097

摘要： A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

摘要翻译： 描述了一种新颖的双层DRAM架构，其在保持传统折叠架构的噪声性能的同时实现了裸片尺寸的显着降低。 主要通过使用“交叉点”型存储单元布局的6F2或更小的存储单元构建存储器阵列。 存储器阵列利用堆叠数字线和垂直数字线扭转来实现折叠架构操作和噪声性能。

公开(公告)号：US6104209A

公开(公告)日：2000-08-15

申请号：US140857

申请日：1998-08-27

申请人： Brent Keeth ,  Russel J. Baker

发明人： Brent Keeth ,  Russel J. Baker

IPC分类号： G11C7/00 ,  G11C8/00 ,  H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/018528 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  H03K19/00384

摘要： A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

摘要翻译： 用于SynchLink型同步动态随机存取存储器（SLDRAM）的差分时钟接收器包括具有用于偏置其NMOS和PMOS电流源的新颖方法的差分放大器。 由差分放大器接收和放大的差分时钟切换一组多路复用器，其通过输出差分输出时钟来响应。 多路复用器可以通过无效使能信号“禁用”，因此它们为差分输出时钟输出一个恒定的“0”电平。 差分时钟接收器的禁用功能对于SLDRAM中发现的间歇数据时钟特别有用。 此外，差分放大器的电流源的新型偏置方法给时钟接收器非常低的偏移。

公开(公告)号：US6103547A

公开(公告)日：2000-08-15

申请号：US784362

申请日：1997-01-17

申请人： David J. Corisis ,  Brent Keeth

发明人： David J. Corisis ,  Brent Keeth

IPC分类号： H01L23/64 ,  H01L23/66 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/66 ,  H01L23/645 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desired, a semiconductor device retainer, lead frame, and wire bond interconnections.

公开(公告)号：US6101197A

公开(公告)日：2000-08-08

申请号：US933324

申请日：1997-09-18

申请人： Brent Keeth ,  Troy A. Manning

发明人： Brent Keeth ,  Troy A. Manning

IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/13 ,  H03L7/07 ,  H03L7/081 ,  H04J3/06

CPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/131 ,  H03L7/07 ,  H03L7/0812 ,  G11C2207/2281 ,  G11C2207/229

摘要： A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi--tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.

摘要翻译： 可变延迟电路由精细延迟电路和粗略延迟电路构成。 精细延迟电路相对于输入时钟信号以相对小的相位增量调整延迟时钟信号的延迟。 粗延迟电路以相对大的相位增量来调整数字信号的定时。 延迟时钟信号用于对应用数字信号的寄存器进行时钟，以响应于调整精细延迟电路和粗略延迟电路的定时来控制通过寄存器定时的数字信号的定时。 最初通过改变精细延迟电路的延迟来调整定时关系。 每当达到精细延迟电路的最大或最小延迟时，调整粗略延迟电路。 可变延迟电路可以用于存储器件中以控制将读取数据应用于存储器件的数据总线的定时。 精细延迟电路包括耦合到多路复用器的多抽头延迟线，其选择一个抽头用于产生延迟的时钟。 当选择第一或最后一个抽头时，调整粗延迟电路的定时。 粗延迟电路包括从初始计数到终端计数的计数时产生数字信号的计数器。 通过调整计数器的初始计数来调整粗略延迟电路。

公开(公告)号：US6097647A

公开(公告)日：2000-08-01

申请号：US382526

申请日：1999-08-25

申请人： Paul S. Zagar ,  Brent Keeth ,  Adrian E. Ong

发明人： Paul S. Zagar ,  Brent Keeth ,  Adrian E. Ong

IPC分类号： G06F12/16 ,  G01R31/30 ,  G06F11/22 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/44 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/70 ,  G01R31/3004 ,  G06F11/22 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50 ,  G11C29/83 ,  G11C29/832 ,  G11C29/88 ,  G11C11/401 ,  G11C2029/5006

摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

摘要翻译： 集成电路存储器件具有多个子阵列分隔，其可以独立地与集成电路上的剩余电路隔离。 集成电路的子阵列可以独立测试。 如果发现集成电路的子阵列不可操作，则它与集成电路上的剩余电路电隔离，使得其不能干扰剩余电路的正常操作。 以前曾经是灾难性的子阵列中的诸如地面短路的电力的缺陷可以电隔离，允许利用剩余的功能子阵列。 通过隔离不起作用元件的集成电路修复消除了以前与集成电路相关的电流消耗和其他性能下降，缺陷通过单独使用冗余元件进行维修。

公开(公告)号：US6084307A

公开(公告)日：2000-07-04

申请号：US211662

申请日：1998-12-15

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L27/10

CPC分类号： H01L27/10885 ,  H01L23/5225 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/907 ,  Y10S257/908

摘要： There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F.sup.2) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

公开(公告)号：US6029250A

公开(公告)日：2000-02-22

申请号：US150079

申请日：1998-09-09

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G06F5/06 ,  G06F1/04

CPC分类号： G06F5/06

摘要： A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to store the digital signal responsive to the clock signal. The digital signal is applied to the latch, and stored in the latch responsive to the clock signal. The digital signal stored in the latch is evaluated to determine if the stored digital signal has an expected value. The timing offset of the digital signal is thereafter adjusted relative to the clock signal. and the digital signal is once again stored in the latch responsive to the clock signal at the new timing offset. A number of digital signals at respective timing offsets relative to the clock signal are stored and evaluated, and a final timing offset of the digital signal is selected from the ones of the timing offsets that cause the latch to store the digital signal having the expected value. The timing offset of the digital signal is thereafter adjusted to the selected final timing offset. A read synchronization circuit may adaptively adjust the timing offset of digital signals in this manner, and such a read synchronization circuit may be utilized in many types of integrated circuits, including packetized dynamic random access memories, memory systems including a memory controller and one or more such packetized dynamic random access memories, and in computer systems including a plurality of such packetized dynamic random access memories.

摘要翻译： 方法和电路自适应地调整数字信号相对于与该数字信号一致的时钟信号输出的定时偏移，以使锁存器接收数字信号以响应于时钟信号存储数字信号。 数字信号被施加到锁存器，并且响应于时钟信号而存储在锁存器中。 评估存储在锁存器中的数字信号，以确定所存储的数字信号是否具有期望值。 此后，数字信号的定时偏移相对于时钟信号进行调整。 并且响应于新定时偏移处的时钟信号，数字信号再次存储在锁存器中。 存储和评估相对于时钟信号的相应定时偏移处的多个数字信号，并且从引起锁存器存储具有期望值的数字信号的定时偏移中选择数字信号的最终定时偏移 。 此后，数字信号的定时偏移被调整到所选择的最终定时偏移。 读取同步电路可以以这种方式自适应地调整数字信号的定时偏移，并且这种读取同步电路可用于许多类型的集成电路，包括分组化的动态随机存取存储器，包括存储器控制器和一个或多个 这种分组化动态随机存取存储器，以及包括多个这样的分组化动态随机存取存储器的计算机系统中。

公开(公告)号：US5949254A

公开(公告)日：1999-09-07

申请号：US757738

申请日：1996-11-26

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G11C11/417 ,  G11C11/409 ,  G11C16/06 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018585 ,  H03K19/00361

摘要： An output driver circuit offers wave-shaping and logic level adjustment for high speed data communications in a synchronous memory such as a dynamic random access memory (DRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Wave-shaping functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different wave-shaping characteristics of the output signal.

摘要翻译： 输出驱动器电路为诸如动态随机存取存储器（DRAM）的同步存储器中的高速数据通信提供波形整形和逻辑电平调整。 电平调节通过端接电阻之间的电阻分压和输出节点与VDD和VSS电源之间的可控阻抗获得。 波形整形功能包括响应于输入信号中的转变顺序地导通或关闭输出晶体管，在输出节点处的信号的转换速率修正。 输出晶体管的不同加权方案获得了输出信号的不同波形整形特性。

公开(公告)号：US5917758A

公开(公告)日：1999-06-29

申请号：US743614

申请日：1996-11-04

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： H03K17/16 ,  G11C7/00 ,  H03K5/12

CPC分类号： H03K17/164

摘要： An adjustable integrated circuit output driver circuit is described which has a push-pull output circuit comprised of a pullup and pulldown transistor. A series of parallel transistors are connected to both the pullup and pulldown transistors. The gates of the parallel transistors are selectively controlled to adjust the driver current connected to a data bus line. Adjustable slew rate control circuits are described which are coupled to the pullup and pulldown transistors. Slew rate control circuitry and output control circuitry is provided to selectively adjust the driver circuit either during manufacture or after installation on a data bus. An alternate open-drain adjustable output driver circuit is also described.

摘要翻译： 描述了一种可调整的集成电路输出驱动器电路，其具有由上拉和下拉晶体管组成的推挽输出电路。 一系列并联晶体管连接到上拉和下拉晶体管。 选择性地控制并联晶体管的栅极以调节连接到数据总线的驱动电流。 描述了可调节的转换速率控制电路，其耦合到上拉和下拉晶体管。 提供压摆率控制电路和输出控制电路以在制造期间或在数据总线上安装之后选择性地调节驱动电路。 还描述了另外的开漏可调输出驱动电路。

公开(公告)号：US5914968A

公开(公告)日：1999-06-22

申请号：US885681

申请日：1997-06-30

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G01R31/317 ,  G06F11/22 ,  G06F11/00

CPC分类号： G06F11/2273 ,  G01R31/31701

摘要： The method for initiating and controlling integrated circuit testing includes providing a plurality of test modes with each test mode having a corresponding test mode address vector. A test enable cycle is enabled by executing an unlock enable cycle with a predetermined lockout address vector and at least one particular test mode of the plurality of test modes is initiated by executing the test enable cycle with a test mode address vector corresponding to the at least one particular test mode. The method may also include latching the at least one particular test mode of the plurality of test modes, detecting supply voltage applied to the integrated circuit, and clearing the latched at least one particular test mode as a function of the detected supply voltage. The test enable cycle may also include a supervoltage test enable cycle executable with a supervoltage.

摘要翻译： 用于启动和控制集成电路测试的方法包括提供多个测试模式，每个测试模式具有相应的测试模式地址向量。 通过执行具有预定的锁定地址向量的解锁使能周期来启用测试使能周期，并且通过执行具有与至少对应的测试模式地址向量的测试使能周期来启动多个测试模式中的至少一个特定测试模式 一个特定的测试模式。 该方法还可以包括锁存多个测试模式中的至少一个特定测试模式，检测施加到集成电路的电源电压，以及根据检测到的电源电压清除锁存的至少一个特定测试模式。 测试使能周期还可以包括可执行超电压的超电压测试使能周期。