公开(公告)号：US20070288436A1

公开(公告)日：2007-12-13

申请号：US11751802

申请日：2007-05-22

申请人： Yu Cao

发明人： Yu Cao

IPC分类号： G06F17/30

CPC分类号： G06F17/30864 ,  Y10S707/99935

摘要： Methods and apparatus that deliver a searching experience that is substantially akin to consultation with a human expert, and that satisfies a user's information need in fulfilling projects such as purchasing, shopping, procurement, bartering, requesting for quotes, in online retail, traditional retail, wholesale, health care, travel, real estate, restaurant-going, entertainment, logistics, and sourcing are disclosed. Search results often contain entities that provide services and products. Records being searched are associated with industry sectors in a broad sense. Industry sector information is first derived from a user query; and is used in determining relevant and adequate additional questions for a searcher, and in matching, ranking, and presenting search results.

摘要翻译： 提供与人类专家咨询基本相似的搜索体验的方法和设备，满足用户在购买，购物，采购，易货，请求报价，在线零售，传统零售， 披露了批发，保健，旅游，房地产，餐饮，娱乐，物流和采购。 搜索结果通常包含提供服务和产品的实体。 正在搜索的记录与广义上的行业有关。 行业信息首先从用户查询中导出; 并用于确定搜索者的相关和足够的附加问题，以及匹配，排名和呈现搜索结果。

公开(公告)号：US20070288422A1

公开(公告)日：2007-12-13

申请号：US11752205

申请日：2007-05-22

申请人： Yu Cao

发明人： Yu Cao

IPC分类号： G06F17/30

CPC分类号： G06F17/30241 ,  Y10S707/99935

摘要： A system that automatically discerning the best combinations of a user query's geographical origin and language, retrieving and displaying search results accordingly. A record on the system are associated with a geographic location and a language. A record could be composed of two or more records, each of which associates with a location and a language. A record could be in rich media format.

摘要翻译： 自动识别用户查询的地理来源和语言的最佳组合的系统，相应地检索和显示搜索结果。 系统上的记录与地理位置和语言相关联。 记录可以由两个或多个记录组成，每个记录与位置和语言相关联。 记录可以是富媒体格式。

公开(公告)号：US20070035727A1

公开(公告)日：2007-02-15

申请号：US11584714

申请日：2006-10-19

申请人： George Chen ,  Lih-Huah Yiin ,  Yu Cao

发明人： George Chen ,  Lih-Huah Yiin ,  Yu Cao

IPC分类号： G01N21/88

CPC分类号： G01N21/9501 ,  G01N21/956

摘要： A method and apparatus for inspecting specimens or patterned transmissive substrates, such as photomasks, for unwanted particles and features, particularly those associated with contacts, including irregularly shaped contacts. A specimen is illuminated by a laser through an optical system comprised of a laser scanning system, individual transmitted and/or reflected light collection optics and detectors collect and generate signals representative of the light transmitted by the substrate. The defect identification of the substrate is performed using those transmitted light signals. Defect identification is performed using an inspection algorithm by comparing image feature representations of a test specimen with a reference specimen, and using a boundary computer and flux comparison device to establish tight boundaries around contacts and compute flux differences between the test and reference specimen contacts. Defect sizes are reported as ratio of flux difference, and entire contacts are highlighted for review.

摘要翻译： 用于检查样品或图案化的透射基底（例如光掩模）的方法和装置，用于不期望的颗粒和特征，特别是与触点相关联的那些，包括不规则形状的触点。 通过由激光扫描系统，单独发射和/或反射光收集光学器件组成的光学系统，激光照射样品，并且检测器收集并产生表示由衬底透射的光的信号。 使用这些透射光信号进行衬底的缺陷识别。 通过比较测试样本的图像特征表示和参考样本，并使用边界计算机和通量比较装置在接触周围建立紧密的边界并计算测试和参考样本接触之间的通量差，使用检查算法执行缺陷识别。 缺陷尺寸报告为通量差的比率，并且整个触点被突出显示以供审查。

公开(公告)号：US20070035712A1

公开(公告)日：2007-02-15

申请号：US11462022

申请日：2006-08-02

申请人： Michael Gassner ,  Stefan Hunsche ,  Yu Cao ,  Jun Ye ,  Moshe Preil

发明人： Michael Gassner ,  Stefan Hunsche ,  Yu Cao ,  Jun Ye ,  Moshe Preil

IPC分类号： G03B27/52

CPC分类号： G03F7/70666 ,  G03F7/70641

摘要： A method of using an in-situ aerial image sensor array is disclosed to separate and remove the focal plane variations caused by the image sensor array non-flatness and/or by the exposure tool by collecting sensor image data at various nominal focal planes and by determining best focus at each sampling location by analysis of the through-focus data. In various embodiments, the method provides accurate image data at best focus anywhere in the exposure field, image data covering an exposure-dose based process window area, and a map of effective focal plane distortions. The focus map can be separated into contributions from the exposure tool and contributions due to topography of the image sensor array by suitable calibration or self-calibration procedures. The basic method enables a wide range of applications, including for example qualification testing, process monitoring, and process control by deriving optimum process corrections from analysis of the image sensor data.

摘要翻译： 公开了一种使用原位空间图像传感器阵列的方法，以分离和去除由图像传感器阵列非平坦度引起的焦平面变化和/或通过曝光工具通过在各种标称焦平面处收集传感器图像数据，并且通过 通过分析焦点数据确定每个采样位置的最佳焦点。 在各种实施例中，该方法在曝光区域的任何地方提供最佳焦点上的精确图像数据，覆盖基于曝光剂量的过程窗口区域的图像数据和有效焦平面失真的映射。 焦点图可以通过适当的校准或自校准程序分为曝光工具的贡献和由于图像传感器阵列的形貌造成的贡献。 基本方法可以通过从图像传感器数据分析中得出最佳的过程校正，实现广泛的应用，包括例如鉴定测试，过程监控和过程控制。

公开(公告)号：US07117478B2

公开(公告)日：2006-10-03

申请号：US11037988

申请日：2005-01-18

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G06F19/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US20050122500A1

公开(公告)日：2005-06-09

申请号：US11037988

申请日：2005-01-18

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G03B27/54 ,  G03F20060101 ,  G03F7/20 ,  G06F17/50 ,  G06K9/00 ,  G06T7/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US20050097500A1

公开(公告)日：2005-05-05

申请号：US10981914

申请日：2004-11-04

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G03B27/54 ,  G03F20060101 ,  G03F7/20 ,  G06F17/50 ,  G06K9/00 ,  G06T7/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US11546937B2

公开(公告)日：2023-01-03

申请号：US17088802

申请日：2020-11-04

申请人： Yu Cao ,  Amine Maaref

发明人： Yu Cao ,  Amine Maaref

IPC分类号： H04W4/00 ,  H04W72/14 ,  H04W72/04 ,  H04L1/18 ,  H04W92/18

摘要： Methods and systems are provided that facilitate sidelink (SL) retransmission scheduled by the network if a SL transmission of a transport block (TB) is unsuccessful. Signalling is used by the network to send a configured grant of transmission resources available for SL transmissions by the UE that repeat on a periodic basis within each of period. The UE makes SL transmissions during one of the periods by transmitting one or more SL transmissions of at least one transport block using the configured resources. The network can schedule a retransmission by transmitting a downlink control information (DCI) to schedule a SL retransmission of one of the transmitted TB. The UE transmits a SL transmission containing a retransmission of the transport block using resources specified in the DCI. The UE transmits a sidelink control information associated with each SL transmission, containing a HARQ process ID for the SL transmission.

公开(公告)号：US20160336064A1

公开(公告)日：2016-11-17

申请号：US15156113

申请日：2016-05-16

申请人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

发明人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

IPC分类号： G11C13/00 ,  G06N3/08

CPC分类号： G06N3/088 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0069

摘要： Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

摘要翻译： 公开了包括交叉点电阻网络和线路控制电路的神经计算电路。 交叉点电阻网络包括可变电阻单元。 一组可变电阻单元被配置为在导线上产生校正线电流，而其他组的可变电阻单元在其它导线上产生合成线电流。 线路控制电路被配置为从导线接收线电流并产生数字矢量值。 根据对应的合成线电流的电流电平和校正线电流的电流电平之间的差，提供每个数字矢量值。 以这种方式，通过校正线电流的当前电平来校正数字矢量值，以便减少由有限导通到导通状态比率导致的误差。

公开(公告)号：US20140223517A1

公开(公告)日：2014-08-07

申请号：US14127467

申请日：2012-07-11

申请人： Zhibo Zhang ,  Yanjun Xu ,  Changsheng Shan ,  Xiaobin Yu ,  Wenwen Yu ,  Yu Cao

发明人： Zhibo Zhang ,  Yanjun Xu ,  Changsheng Shan ,  Xiaobin Yu ,  Wenwen Yu ,  Yu Cao

IPC分类号： H04L29/06

CPC分类号： H04L63/10 ,  G06K7/10247 ,  G06K19/07732 ,  G06K19/07733

摘要： A device for processing and storing data is disclosed, which comprises a primary controller, a primary memory, a security element (SE), and at least one universal port, wherein the device for processing and storing data further includes a first additional port, via which the security element (SE) can directly interacts with a second external device to complete the processing and access of the data. The security element (SE) in the device for processing and storing data disclosed herein can work independently without being effected by the condition whether the primary memory is performing the data read/write process, and supports the single wire protocol (SWP).

摘要翻译： 公开了一种用于处理和存储数据的设备，其包括主控制器，主存储器，安全元件（SE）和至少一个通用端口，其中用于处理和存储数据的设备还包括第一附加端口，经由 安全元件（SE）可以直接与第二外部设备交互以完成数据的处理和访问。 用于处理和存储本文公开的数据的设备中的安全元件（SE）可以独立地工作，而不受主存储器是否执行数据读/写过程的条件的影响，并且支持单线协议（SWP）。