中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

178 records (took 0.024 seconds)

    Layer formation with reduced channel loss
    131.
    发明授权
    Layer formation with reduced channel loss 有权
    层形成减少了通道损耗

    公开(公告)号：US09000491B2

    公开(公告)日：2015-04-07

    申请号：US14309409

    申请日：2014-06-19

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

    IPC: H01L29/745 ,  H01L27/148 ,  H01L21/311 ,  H01L29/10 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

    Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

    Abstract translation: 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

    Method of making a semiconductor device using sacrificial fins
    132.
    发明授权
    Method of making a semiconductor device using sacrificial fins 有权
    制造使用牺牲散热片的半导体器件的方法

    公开(公告)号：US08987082B2

    公开(公告)日：2015-03-24

    申请号：US13906758

    申请日：2013-05-31

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Prasanna Khare

    IPC: H01L21/8238 ,  H01L21/8234

    CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878

    Abstract: A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.

    Abstract translation: 制造半导体器件的方法包括在半导体层上形成牺牲层。 牺牲层的一部分被选择性地去除以在半导体层的第一区域上限定出第一组隔开的牺牲散热片，以及在半导体层的第二区域上的第二组隔开的牺牲散热片。 在第一和第二区域之间的半导体层中形成隔离沟槽。 绝缘沟槽和空间填充有电介质材料。 去除第一组和第二组牺牲翅片以限定相应的第一组和第二组翅片开口。 填充第一组翅片开口以限定用于第一导电型晶体管的第一组半导体鳍片，并且填充第二组翅片开口以限定用于第二导电型晶体管的第二组半导体鳍片。

    Method for the formation of a protective dual liner for a shallow trench isolation structure
    134.
    发明授权
    Method for the formation of a protective dual liner for a shallow trench isolation structure 有权
    用于形成浅沟槽隔离结构的保护性双层衬垫的方法

    公开(公告)号：US08962430B2

    公开(公告)日：2015-02-24

    申请号：US13907237

    申请日：2013-05-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Qing Liu ,  Nicolas Loubet ,  Bruce Doris

    IPC: H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/66477 ,  H01L21/76232 ,  H01L21/76283 ,  H01L29/0649

    Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.

    Abstract translation: 在由第一半导体层，绝缘层和第二半导体层形成的衬底上，沉积氧化硅衬垫层和氮化硅衬垫层以形成掩模。 掩模用于打开通过第一半导体层和绝缘层并进入第二半导体层的沟槽。 二氧化硅和氮化硅的双衬垫共形沉积在沟槽内。 沟槽填充有二氧化硅。 氢氟酸蚀刻将氮化硅衬垫层与一部分共形氮化硅衬垫一起去除。 热磷酸蚀刻去除氧化硅衬垫层，填充沟槽的氧化硅的一部分和保形氮化硅衬垫的一部分。 双衬垫在第一和第二半导体层之间的沟槽的边缘处防止衬底蚀刻。

    BULK FINFET SEMICONDUCTOR-ON-NOTHING INTEGRATION
    135.
    发明申请
    BULK FINFET SEMICONDUCTOR-ON-NOTHING INTEGRATION 有权
    大容量FINFET半导体无关集成

    公开(公告)号：US20150041898A1

    公开(公告)日：2015-02-12

    申请号：US13964009

    申请日：2013-08-09

    Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Jin Cho

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L29/785

    Abstract: Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.

    Abstract translation: 描述了以体半导体衬底开始形成完全绝缘的finFET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 第一外延层可以是牺牲的。 可以在翅片结构周围形成最终的栅极结构，并且去除第一外延层以在翅片和衬底之间形成空隙。 空隙可以填充绝缘体以使翅片完全绝缘。

    TRANSISTOR HAVING A STRESSED BODY
    136.
    发明申请
    TRANSISTOR HAVING A STRESSED BODY 审中-公开
    具有受压身体的晶体管

    公开(公告)号：US20150008521A1

    公开(公告)日：2015-01-08

    申请号：US14494979

    申请日：2014-09-24

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

    IPC: H01L29/78 ,  H01L21/266 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06

    CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

    Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

    Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

    FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED OVERLAP CAPACITANCE AND ENHANCED MECHANICAL STABILITY
    137.
    发明申请
    FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED OVERLAP CAPACITANCE AND ENHANCED MECHANICAL STABILITY 有权
    具有降低的覆盖电容的Fin场效应晶体管器件和增强的机械稳定性

    公开(公告)号：US20140353753A1

    公开(公告)日：2014-12-04

    申请号：US13906677

    申请日：2013-05-31

    Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan

    IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7848 ,  H01L29/785

    Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.

    Abstract translation: 改进的鳍状场效应晶体管（FinFET）器件及其制造方法。 一方面，一种用于制造FinFET器件的方法包括：提供生长有硅外延层的硅衬底。 衬底上的牺牲结构由外延层形成。 在牺牲结构和暴露的衬底部分之上形成覆盖硅层，所述覆盖硅层具有均匀厚度的上部和下部，并且中间部分插入在不均匀厚度的上部和下部之间并且具有形成角度。 半导体散热片阵列由覆盖硅层和覆盖层上形成的非共形层形成。 去除牺牲结构，并且在通道区域下填充隔离结构的所得空隙。 在FinFET的鳍合并期间，在源极/漏极区域中形成源极和漏极。

Patent Agency Ranking