公开(公告)号：US20200152282A1

公开(公告)日：2020-05-14

申请号：US16189200

申请日：2018-11-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US20200090770A1

公开(公告)日：2020-03-19

申请号：US16143916

申请日：2018-09-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: Disclosed herein is related to a system and a method of adjusting a programming pulse for programming memory cells. In one aspect, the system includes a controller that iteratively applies a programming pulse to the memory cells during programming loops. The programming pulse has progressively increasing magnitudes to program different subsets of the memory cells to corresponding target states. The controller determines that a programming loop to program a subset of the memory cells targeted to have a corresponding target state of the target states is performed. The controller counts a number of memory cells of the subset that have not reached the target state. The controller determines a magnitude for a programming pulse to be applied for a subsequent programming loop based on the counted number, and applies, during the subsequent programming loop, the programming pulse with the determined magnitude.

公开(公告)号：US10482985B2

公开(公告)日：2019-11-19

申请号：US16017996

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  H01L27/1157 ,  G11C11/56

Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.

公开(公告)号：US12243591B2

公开(公告)日：2025-03-04

申请号：US17896587

申请日：2022-08-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Jiacen Guo ,  Takayuki Inoue

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

公开(公告)号：US12229415B2

公开(公告)日：2025-02-18

申请号：US18346345

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Wei Cao ,  Jiacen Guo ,  Xiang Yang

IPC: G06F3/06

Abstract: In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory cell selected for data sanitation, prior to applying a programming pulse to the corresponding word line, a soft erase operation is performed. After biasing the memory cells and select gates of the NAND strings to a low voltage, a soft erase voltage pulse is applied to the source lines and bit line to pre-charge the NAND string channels with holes.

公开(公告)号：US20240347122A1

公开(公告)日：2024-10-17

申请号：US18754911

申请日：2024-06-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Luca Fasoli

IPC: G11C29/10 ,  G06F11/10

CPC classification number: G11C29/10 ,  G06F11/1044

Abstract: A memory package includes a plurality of memory dies, each of which has a plurality of memory blocks with arrays of memory cells. The memory dies include user data dies that contain user data and an XOR die that contains XOR data. The memory package also includes circuitry for reading the user data and the XOR data. The circuitry is configured to detect a read error during a read operation in a failed die of the plurality of user data dies and read some of the user data of the user data dies besides the failed die and reading some of the XOR data of the XOR die. The circuitry is also configured to perform a read recovery operation that includes an XOR operation using, as inputs, the user data of the user data dies besides the failed die and the XOR data of the XOR die.

公开(公告)号：US12112800B2

公开(公告)日：2024-10-08

申请号：US17825048

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Muhammad Masuduzzaman ,  Jiacen Guo

IPC: G11C11/04 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.

公开(公告)号：US20240319888A1

公开(公告)日：2024-09-26

申请号：US18346345

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Wei Cao ,  Jiacen Guo ,  Xiang Yang

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory cell selected for data sanitation, prior to applying a programming pulse to the corresponding word line, a soft erase operation is performed. After biasing the memory cells and select gates of the NAND strings to a low voltage, a soft erase voltage pulse is applied to the source lines and bit line to pre-charge the NAND string channels with holes.

公开(公告)号：US12046302B2

公开(公告)日：2024-07-23

申请号：US17557492

申请日：2021-12-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/3454 ,  G11C16/08 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3409

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

公开(公告)号：US11972819B2

公开(公告)日：2024-04-30

申请号：US17872148

申请日：2022-07-25

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24

Abstract: In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.