公开(公告)号：US20100165754A1

公开(公告)日：2010-07-01

申请号：US12646827

申请日：2009-12-23

Applicant: Siddharth Gupta ,  Rakesh Kumar Sinha ,  Vamsi Krishna Gullapalli ,  Dibya Dipti

Inventor： Siddharth Gupta ,  Rakesh Kumar Sinha ,  Vamsi Krishna Gullapalli ,  Dibya Dipti

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C7/08 ,  G11C11/413

Abstract: A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.

Abstract translation: 一种用于改善穿过多个电压域的多个信号路径中的信号同步的系统和方法。 根据本公开的实施例，存储器装置优选用于信号同步。 所有读/写和时钟信号和其他控制信号被驱动到周边电源（Vp）电平，除了以核心电源（Vc）电平驱动的字线（WL [i]）信号。 通过这样做，与核心供应（Vc）相关的较低的平均和峰值电流消耗是通过恒定的延迟实现的，并且在穿过多个电压域的信号路径中保持所需的信号同步。

公开(公告)号：US20100164547A1

公开(公告)日：2010-07-01

申请号：US12648075

申请日：2009-12-28

Applicant: Luca Ciccarelli ,  Lorenzo Cali ,  Massimiliano Innocenti ,  Claudio Mucci ,  Valentina Nardone ,  Matteo Pizzotti ,  Pankaj Rohilla

Inventor： Luca Ciccarelli ,  Lorenzo Cali ,  Massimiliano Innocenti ,  Claudio Mucci ,  Valentina Nardone ,  Matteo Pizzotti ,  Pankaj Rohilla

IPC: H01L25/00

CPC classification number: G06F17/5068 ,  H01L27/0207 ,  H01L27/11807

Abstract: A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.

Abstract translation: 一种用于具有至少第一对CMOS晶体管和第二对CMOS晶体管的工程变更单（ECO）实现的基本单元，其特征在于，所述至少第一对CMOS晶体管具有公共栅极和所述至少第二对 的CMOS晶体管具有分离的栅极。

公开(公告)号：US20100157708A1

公开(公告)日：2010-06-24

申请号：US12643520

申请日：2009-12-21

Applicant: Ashish Kumar ,  Manish Umedlal Patel

Inventor： Ashish Kumar ,  Manish Umedlal Patel

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/00 ,  G11C7/065 ,  G11C8/12 ,  G11C2207/005

Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.

Abstract translation: 已经公开了一种用于感测电路的装置和方法。 在实现中，感测电路包括读出放大器和至少一个解耦装置。 解耦器件通过至少一个参考线耦合到读出放大器。 读出放大器读取数据值，去耦器件在读取操作期间将读出放大器与电源解耦。

公开(公告)号：US20100156496A1

公开(公告)日：2010-06-24

申请号：US12343773

申请日：2008-12-24

Applicant: Vikas RANA ,  Abhishek LAL ,  Promod KUMAR

Inventor： Vikas RANA ,  Abhishek LAL ,  Promod KUMAR

IPC: H03L5/00

CPC classification number: H03K3/356113 ,  H03K3/0375 ,  H03K3/356182

Abstract: The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level. The module further comprises a switching circuit that is operatively coupled to the driver output for controlling the passing of a high voltage with high current requirements.

Abstract translation: 本发明公开了一种在其驱动器输出级具有减小的应力的高压开关模块，其继而控制需要高电流驱动的晶体管的栅极。 开关模块包括负升压电路，延迟模块，上拉电路和下拉电路。 负升压电路感测逻辑输入信号的转变以产生控制信号。 第一上拉电路可操作地耦合到该控制信号，用于将驱动器输出从负电压切换到接地电压。 还有一个额外的延迟模块被配置为提供逻辑输入信号的延迟。 该延迟逻辑输入信号可操作地耦合到将驱动器的输出从GND到VDD的第二上拉级。 下拉电路可操作地耦合到负电梯，以将驱动器输出处的电压控制到负电平。 该模块还包括可操作地耦合到驱动器输出的开关电路，用于以高电流要求控制高电压的通过。

公开(公告)号：US20100149884A1

公开(公告)日：2010-06-17

申请号：US12616296

申请日：2009-11-11

Applicant: Ashish Kumar

Inventor： Ashish Kumar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: The present disclosure relates to a system comprising memory device with a power switch where the system comprises a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core; a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core; a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and a second reference voltage coupled to the substrate terminal of said second voltage controlled switch. This helps maintain a sufficient RNM for efficient performance by the system.

Abstract translation: 本公开涉及包括具有电力开关的存储器件的系统，其中该系统包括将正电源耦合到存储器件芯的正电源端的第一电压控制开关; 将负电源耦合到存储器件芯的负电源端的第二压控开关; 耦合到所述第一电压控制开关的衬底端子的第一参考电压; 以及耦合到所述第二电压控制开关的衬底端子的第二参考电压。 这有助于维持足够的RNM以实现系统的高效性能。

公开(公告)号：US07737780B2

公开(公告)日：2010-06-15

申请号：US11900917

申请日：2007-09-12

Applicant: Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Arnold James D'Souza

Inventor： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Arnold James D'Souza

IPC: H03F3/45

CPC classification number: H03F3/45188 ,  H03F3/45677 ,  H03F2203/45052 ,  H03F2203/45074 ,  H03F2203/45248 ,  H03F2203/45296 ,  H03F2203/45302 ,  H03F2203/45318 ,  H03F2203/45342 ,  H03F2203/45356

Abstract: Embodiments of the present invention disclose operational amplifiers which demonstrate good settling behavior with minimum over-shoot or ringing for improving settling behavior. The amplifiers include one or more amplification stages connected to form a symmetric structure. The amplification stage includes a boosting amplifier, a MOS transistor and a compensation capacitor. The MOS transistor can be an NMOS transistor and a PMOS transistor. Using this scheme pole-zero doublets are rearranged in a manner to improve the transient settling response.

Abstract translation: 本发明的实施例公开了运行放大器，其以最小的过冲或振铃来表现出良好的沉降行为，以改善沉降行为。 放大器包括一个或多个连接以形成对称结构的放大级。 放大级包括升压放大器，MOS晶体管和补偿电容器。 MOS晶体管可以是NMOS晶体管和PMOS晶体管。 使用该方案，极点双重重排以改善瞬态稳定响应的方式。

公开(公告)号：US20100146472A1

公开(公告)日：2010-06-10

申请号：US12630576

申请日：2009-12-03

Applicant: Himanshu Srivastava ,  Jyoti Malhotra

Inventor： Himanshu Srivastava ,  Jyoti Malhotra

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A routing system is improved by performing three steps sequentially to complete an execution process. The first step estimates a normalized criticality score for each design net. The second step arranges the scores for each design net in descending order. Third step rips up and reroutes the design so as to make it more feasible.

Abstract translation: 通过顺序执行三个步骤来完成路由系统以完成执行过程。 第一步估计每个设计网络的归一化临界评分。 第二步按降序排列每个设计网的分数。 第三步破解设计，重新设计，使之更可行。

公开(公告)号：US07701261B2

公开(公告)日：2010-04-20

申请号：US11766275

申请日：2007-06-21

Applicant: Saurabh Saxena

Inventor： Saurabh Saxena

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K19/0005 ,  H03K17/145

Abstract: A CMOS Output Buffer providing controlled output impedance includes three internal sections each of which provides a impedance control for a corresponding region of the output V-I characteristics of deep linear, deep saturation and transition regions. Each internal section includes controlled current sinks/current sources enabled to provide a precise control over the DC impedance of the driver across the PAD voltage range.

Abstract translation: 提供受控输出阻抗的CMOS输出缓冲器包括三个内部部分，每个内部部分为深线性，深度饱和和过渡区域的输出V-I特性的对应区域提供阻抗控制。 每个内部部分包括受控的电流吸收/电流源，可以在PAD电压范围内精确控制驱动器的直流阻抗。

公开(公告)号：US07689635B2

公开(公告)日：2010-03-30

申请号：US11260863

申请日：2005-10-27

Applicant: Shalini Gupta ,  Sumanta Sarkar

Inventor： Shalini Gupta ,  Sumanta Sarkar

IPC: G06F7/00

CPC classification number: G06F5/015 ,  G06F7/762 ,  G06F7/768

Abstract: An area efficient data shifter/rotator using a barrel shifter. The invention is a circuit, which uses a single barrel shifter and is controllable to implement either a left or right shift or rotation of bits of a digital data word. The circuit is dynamically controllable to implement left or right shift of bits of the digital data word (both logical and arithmetic) and rotation (to the left or right) of bits of the word. The proposed circuit produces the required output in a single cycle.

Abstract translation: 一种使用桶形移位器的区域高效数据移位器/旋转器。 本发明是一种电路，其使用单个桶形移位器并且可控制地实现数字数据字的位的左移或右移或旋转。 该电路是可动态控制的，以实现数字数据字（逻辑和运算）和字的位（左或右）的位的左移或右移。 所提出的电路在单个周期中产生所需的输出。

公开(公告)号：US07663415B2

公开(公告)日：2010-02-16

申请号：US11649747

申请日：2007-01-03

Applicant: Kallol Chatterjee ,  Nitin Agarwal

Inventor： Kallol Chatterjee ,  Nitin Agarwal

IPC: H03L7/06

CPC classification number: H03L1/022 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099

Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Abstract translation: 锁相环（PLL）架构提供跨工艺和温度的压控振荡器（VCO）增益补偿。 可以使用模拟器来计算用于处理和温度转角的每个组合的VCO的最大和最小输出频率的控制电压。 然后从这些控制电压中选择控制电压的最大值和最小值。 使用计数器，在PLL输入时钟的一些周期中，VCO的周期数以二进制形式计数，并存储在用于极端控制电压的锁存器中。 它们之间的差异与典型工艺和温度角的相应差异用于修改电荷泵以改变递送到环路滤波器的电流。 电荷泵位决定后，VCO的输入控制电压连接到电荷泵输出，开始PLL的正常工作。