公开(公告)号：US20140340150A1

公开(公告)日：2014-11-20

申请号：US14185701

申请日：2014-02-20

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dennis A. Dempsey ,  Sean Brennan ,  Colin Lyden ,  John Jude O'Donnell

IPC: H03F3/45

CPC classification number: H03F1/223 ,  H03F3/45475 ,  H03F2200/156 ,  H03F2203/45116 ,  H03F2203/45528 ,  H03F2203/45536 ,  H03F2203/45696 ,  H03M1/765 ,  H03M1/808

Abstract: An example transconductance circuit is provided in accordance with one embodiment. The transconductance circuit can comprise: an output node; at least one transistor; a variable resistance; and a differential amplifier; wherein the at least one transistor and the variable resistance are in series connection with the output node, an output of the differential amplifier is connected to a control node of the at least one transistor, a first input of the amplifier is responsive to an input signal, and a second input of the amplifier is responsive to a voltage across the variable resistance. Such a circuit may overcome noise problems in transconductance circuits which operate over a wide range of input signals with a fixed resistor in series with the at least one transistor.

Abstract translation: 根据一个实施例提供了示例性跨导电路。 跨导电路可以包括：输出节点; 至少一个晶体管; 可变电阻; 和差分放大器; 其中所述至少一个晶体管和所述可变电阻与所述输出节点串联连接，所述差分放大器的输出端连接到所述至少一个晶体管的控制节点，所述放大器的第一输入端响应于输入信号 并且放大器的第二输入响应可变电阻两端的电压。 这种电路可以克服在具有与至少一个晶体管串联的固定电阻器的宽范围的输入信号上工作的跨导电路中的噪声问题。

公开(公告)号：US20140270018A1

公开(公告)日：2014-09-18

申请号：US13844759

申请日：2013-03-15

Applicant: Analog devices Technology

Inventor： Haim Primo ,  Yosef Stein

IPC: H04L25/03

CPC classification number: H04L25/03006 ,  H03D3/009 ,  H03D7/165 ,  H03D2200/0054 ,  H04B1/30 ,  H04L27/3863

Abstract: An electrical circuit includes a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal, an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output, a compensation mixer configured to multiply the first output with a constant factor to generate a second output, a first low pass filter configured to approximately attenuate frequencies in the second output to generate a third output, and a first correcting filter configured to filter the third output to generate a fourth output. The first correcting filter is configured to reduce a channel impulse response mismatch between the first low pass filter and a second low pass filter, which is configured to attenuate frequencies in a Q-channel of the incoming signal. In specific embodiments, the phase shift includes 45°.

Abstract translation: 电路包括配置成产生第一参考信号的本地振荡器和具有与第一参考信号相关的预定相移的第二参考信号，配置为将第一参考信号注入到输入信号并产生第一参考信号的I信道混合器 输出，配置为将第一输出与常数因子相乘以产生第二输出的补偿混合器，被配置为近似地衰减第二输出中的频率以产生第三输出的第一低通滤波器，以及第一校正滤波器， 第三输出产生第四输出。 第一校正滤波器被配置为减少第一低通滤波器和第二低通滤波器之间的信道脉冲响应失配，其被配置为衰减输入信号的Q信道中的频率。 在具体实施例中，相移包括45°。

公开(公告)号：US20140268936A1

公开(公告)日：2014-09-18

申请号：US14051702

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yanfeng Lu ,  Bin Shao

IPC: H02M1/36

CPC classification number: H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K2217/0081

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

Abstract translation: 至少一个实施例提供了一种纳米功率升压调节器从能量收集应用的超低电压（例如0.3V〜0.5V）启动的方法。 该方法不一定需要特殊的过程或任何外部组件，例如机械开关。 启动电路可以包括异步升压电路，用于堆叠功率NMOS晶体管，环形振荡器和/或电荷泵以及相关电路对输出进行充电。

公开(公告)号：US20140268890A1

公开(公告)日：2014-09-18

申请号：US13799492

申请日：2013-03-13

Applicant: Analog Devices Technology

Inventor： Renjian Xie ,  Qingyi Huang ,  Yingyang Ou

IPC: H02M3/335

CPC classification number: H02M3/1582 ,  H02M2001/007 ,  Y10T307/25

Abstract: A switching power converter includes a voltage source that provides an input voltage Vin to an unregulated DC/DC converter stage and at least one buck-boost converter stage to produce a desired output voltage Vout. The unregulated DC/DC converter stage is adapted to provide an isolated voltage to the at least one regulated buck-boost converter stage, wherein the unregulated DC/DC converter stage comprises a transformer having a primary winding and at least one secondary winding and at least one switching element coupled to the primary winding. The at least one buck-boost converter stage is arranged to operate in a buck mode, boost mode or buck-boost mode in response to a mode selection signal from a mode selection module. By influencing the pulse width modulation output power controller the at least one buck-boost converter stage is arranged to produce one or multiple output voltages.

Abstract translation: 开关功率转换器包括向未调节的DC / DC转换器级和至少一个降压 - 升压转换器级提供输入电压Vin以产生期望的输出电压Vout的电压源。 未调节的DC / DC转换器级适于向至少一个调节的降压 - 升压转换器级提供隔离电压，其中未调节的DC / DC转换器级包括具有初级绕组和至少一个次级绕组的变压器，并且至少 一个开关元件耦合到初级绕组。 至少一个降压 - 升压转换器级被布置成响应于来自模式选择模块的模式选择信号而以降压模式，升压模式或降压 - 升压模式操作。 通过影响脉宽调制输出功​​率控制器，至少一个降压 - 升压转换器级布置成产生一个或多个输出电压。

公开(公告)号：US20140266314A1

公开(公告)日：2014-09-18

申请号：US14204851

申请日：2014-03-11

Applicant: Analog Devices Technology

Inventor： Santiago Iriarte ,  John A. Cleary

IPC: H03K5/24

CPC classification number: H03K5/2472

Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.

Abstract translation: 一种电源监视电路，用于监视与参考节点相比的电源节点处的电压，所述电源监视电路包括第一场效应晶体管和第一和第二降压组件，所述第一和第二降压组件以电流节点和 参考节点，并且每个具有第一和第二节点，并且其中第一降压部件的第一节点连接到场效应晶体管的第一和第二节点中的一个，并且场效应晶体管的栅极连接到第二节点 第一降压部件的节点，并且从与第一场效应晶体管制成的连接取得输出信号。

公开(公告)号：US20140253062A1

公开(公告)日：2014-09-11

申请号：US13791234

申请日：2013-03-08

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Song Qin

IPC: G05F1/10

CPC classification number: G05F1/10 ,  H02M1/088 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

Abstract: Apparatus and methods for current sensing in switching regulators are provided. In certain implementations, a switching regulator includes a switch transistor, a replica transistor, a current source, a sense resistor, and a current sensing circuit. The drain and gate of the switch transistor can be electrically connected to the drain and gate of the replica transistor, respectively. Additionally, the current sensing circuit can control the voltage of the source of the replica transistor based on the polarity of a current through the switch transistor to generate an output current that changes in response to the switch transistor's current. The sense resistor can receive an offset current from the first current source and the output current from the current sensing circuit such that the voltage across the sense resistor changes in relation to the current through the switch transistor.

Abstract translation: 提供了开关稳压器中电流检测的装置和方法。 在某些实现中，开关调节器包括开关晶体管，复制晶体管，电流源，检测电阻和电流感测电路。 开关晶体管的漏极和栅极可以分别电连接到复制晶体管的漏极和栅极。 此外，电流感测电路可以基于通过开关晶体管的电流的极性来控制复制晶体管的源的电压，以产生响应于开关晶体管的电流而改变的输出电流。 感测电阻器可以接收来自第一电流源的偏移电流和来自电流感测电路的输出电流，使得感测电阻两端的电压相对于通过开关晶体管的电流而变化。

公开(公告)号：US20140240944A1

公开(公告)日：2014-08-28

申请号：US13776545

申请日：2013-02-25

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Bernard P. Stenson ,  Michael Morrissey ,  Seamus A. Lynch

IPC: B81B7/00

CPC classification number: H01L28/00 ,  H01L27/016 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60

Abstract: A microelectronic circuit having at least one component adjacent a carrier which is not a semiconductor or sapphire.

Abstract translation: 微电子电路具有与不是半导体或蓝宝石的载体相邻的至少一个分量。

公开(公告)号：US20140196540A1

公开(公告)日：2014-07-17

申请号：US13741198

申请日：2013-01-14

Applicant: ANALOG DEVICES, TECHNOLOGY

Inventor： Arturo Martizon, JR. ,  Thomas M. Goida

IPC: H05K1/11 ,  B81C3/00

CPC classification number: B81C3/008 ,  B81B7/0074 ,  H01L23/49555 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10T29/49117 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Vertical mount package assemblies and methods for making the same are disclosed. A method for manufacturing a vertical mount package assembly includes providing a base substrate having electrical connections for affixing to external circuitry, and providing a package having a mounting region configured to receive a device therein. Flexible electrical leads are formed between the base substrate and the package. The flexible leads can include a plurality of aligned grooves to guide bending. After forming the flexible electrical leads, the package is rotated relative to the base substrate. The aligned grooves can constrain the relative positions of the substrates during rotation, and the beveled edges of the base substrate and package can maintain a desired angular relationship (e.g., perpendicular) between the base substrate and the package after rotation.

Abstract translation: 公开了垂直安装的封装组件及其制造方法。 一种用于制造垂直安装封装组件的方法，包括提供具有用于固定到外部电路的电连接的基底基板，以及提供具有被配置为在其中接收设备的安装区域的封装。 柔性电引线形成在基底基板和封装之间。 柔性引线可以包括多个对准的沟槽以引导弯曲。 在形成柔性电引线之后，封装相对于基底基板旋转。 对准的沟槽可以在旋转期间约束衬底的相对位置，并且基底衬底和封装的斜边缘可以在旋转之后保持基底衬底和封装之间的期望的角度关系（例如，垂直）。

公开(公告)号：US08766992B2

公开(公告)日：2014-07-01

申请号：US13892508

申请日：2013-05-13

Applicant: Analog Devices Technology

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thaker

IPC: G06F13/372 ,  G06K9/36 ,  G06K9/64 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，以便即使当处理操作转换到新的像素或新的像素帧时，仍然保持恒定的存储器读取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。

公开(公告)号：US20140133698A1

公开(公告)日：2014-05-15

申请号：US13888993

申请日：2013-05-07

Applicant: Analog Devices Technology

Inventor： Joseph Fernandez ,  Sreenath Kottekkode

IPC: G06K9/00

CPC classification number: G06K9/00805 ,  G06K9/00791 ,  G06K9/4642 ,  G06K9/6269

Abstract: Objects are detected in real-time at full VGA 30 frame per second resolution. A preprocessor performs run-length encoding (RLE) and generates a summed area table (SAT) of an image. The RLE and SAT are used to identify candidate objects and to iteratively refine their boundaries. A histogram of gradients (HoG) and support vector machine (SVM) then reliably classify the object. The method may be part of an advanced driver assistance system (ADAS).

Abstract translation: 实时检测物体的全VGA每秒30帧分辨率。 预处理器执行游程长度编码（RLE）并生成图像的求和区域表（SAT）。 RLE和SAT用于识别候选对象并迭代地改进边界。 梯度（HoG）和支持向量机（SVM）的直方图然后可靠地对对象进行分类。 该方法可以是高级驾驶员辅助系统（ADAS）的一部分。