公开(公告)号：US20190188173A1

公开(公告)日：2019-06-20

申请号：US16273943

申请日：2019-02-12

Applicant: SOCIONEXT INC.

Inventor： Takayuki OTANI ,  Teruhiko KAMIGATA ,  Takashi KAWASAKI ,  Eiichi NIMODA

IPC: G06F13/38 ,  G06F13/16

Abstract: A bus control circuit for transferring an exclusive command between first and second bus specifications by mutually converting a first exclusive command of the first bus specification which deals with an exclusive access, and a second exclusive command of the second bus specification which doesn't deal with the exclusive access, includes an exclusive command conversion circuit receiving the first exclusive command, converting and outputting the second exclusive command, when converting from the first to second exclusive commands; an exclusive command generation circuit receiving the second exclusive command and generating the first exclusive command, when converting from the second to first exclusive commands; an exclusive response issuing circuit issuing exclusive response information for the second exclusive command, when converting from the second to first exclusive commands; and an exclusive response receiving circuit receiving exclusive response information for the second exclusive command, when converting from the first to second exclusive commands.

公开(公告)号：US20190172841A1

公开(公告)日：2019-06-06

申请号：US16269360

申请日：2019-02-06

Applicant: SOCIONEXT INC.

Inventor： Keisuke KISHISHITA

IPC: H01L27/118 ,  H01L27/02

Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. In a standard cell including nanowire FETs connected in series through an intermediate node used only for mutual connection, the nanowire FETs include first, second, and third pads, Na nanowires extending in an X direction between the first and second pads to connect the first and second pads together, and Nb nanowires extending in the X direction between the second and third pads to connect the second and third pads together.

公开(公告)号：US20190171821A1

公开(公告)日：2019-06-06

申请号：US16259884

申请日：2019-01-28

Applicant: Socionext Inc.

Inventor： Kazuya ASANO ,  Yuya UENO ,  Seiji GOTO

IPC: G06F21/57 ,  H04L9/08 ,  G06F9/4401 ,  G06F21/85

Abstract: A semiconductor integrated circuit generates second boot code by encrypting first boot code, and transmits, based on route information indicating a delivery route of the second boot code, encrypted data including the second boot code to a first destination via a network. A different semiconductor integrated circuit is the first destination, and receives the encrypted data via the network and generates third boot code by decrypting the second boot code.

公开(公告)号：US20190165186A1

公开(公告)日：2019-05-30

申请号：US16262309

申请日：2019-01-30

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US10303901B2

公开(公告)日：2019-05-28

申请号：US15340061

申请日：2016-11-01

Applicant: Socionext Inc.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G11C7/00 ,  G06F17/30 ,  G06F13/00 ,  G06F12/14 ,  G06F12/00 ,  G06F7/04 ,  G06F21/74 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/70 ,  G06F21/53 ,  G06F12/1027 ,  G06F13/24

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US20190117122A1

公开(公告)日：2019-04-25

申请号：US16164386

申请日：2018-10-18

Applicant: SOCIONEXT INC.

Inventor： Ryusuke Kurachi ,  Hiroyuki Tomura ,  Masato Yoshioka ,  Masaya Tamamura ,  Amane Inoue

IPC: A61B5/113 ,  H03K3/037 ,  A61B5/11

Abstract: A pulse signal generator circuit generates first and second pulse signals for electrodes placed on the chest of a subject with phases that differ by 180°. A rectifier circuit receives a potential difference signal, which reflects an impedance between the electrodes that changes according to respiratory motion and in which timing of changes caused by changes in the first pulse signal or the second pulse signal is delayed from the timing of the changes in the first pulse signal and the second pulse signal, and outputs a rectified signal produced by rectifying the potential difference signal. A control signal generator circuit causes the rectifier circuit to invert the potential difference signal, which becomes a negative voltage value from the certain timing, to a positive voltage value from the certain timing. An AD converter circuit outputs a digital value based on the magnitude of the rectified signal.

公开(公告)号：US10249606B2

公开(公告)日：2019-04-02

申请号：US15169002

申请日：2016-05-31

Applicant: SOCIONEXT INC.

Inventor： Teruo Suzuki

IPC: H02H9/00 ,  H01L27/02

Abstract: A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a second domain including a second high power source line, a second low power source line, and a second power clamp circuit; a third power clamp circuit provided between the second high power source line and the first low power source line; a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line.

公开(公告)号：US20190052259A1

公开(公告)日：2019-02-14

申请号：US16165431

申请日：2018-10-19

Applicant: SOCIONEXT INC.

Inventor： Masahisa IIDA

IPC: H03K17/16 ,  H03K17/00 ,  H03K19/0185

Abstract: In order to provide a power supply switch circuit using only low-breakdown voltage transistors and eliminate the need for a special through-current preventing circuit, the switch control circuits output a signal ranging from a ground voltage level to a second power supply voltage level when a first power supply voltage (0 V/3.3 V) is in off-state and a second power supply voltage (0 V/1.8 V) is in on-state, and a signal ranging from the second power supply voltage level to a first power supply voltage level when the first and second power supply voltages are in on-state, thereby allowing a PMOS transistor and an NMOS transistor to turn on or off.

公开(公告)号：US20190051601A1

公开(公告)日：2019-02-14

申请号：US16138868

申请日：2018-09-21

Applicant: SOCIONEXT INC.

Inventor： Masanobu HIROSE ,  Toshihiro NAKAMURA

IPC: H01L23/528 ,  H01L23/50 ,  H01L27/02

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects (21a to 21d) provided in I/O cell rows (10A, 10B) are connected to a power supply interconnect (23) provided between the I/O cell rows (10A, 10B) via power supply interconnects (25a to 25d). The power supply interconnect (23) is thicker than the in-row power supply interconnects (21a to 21d).

公开(公告)号：US10181469B2

公开(公告)日：2019-01-15

申请号：US15863107

申请日：2018-01-05

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/118 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.