High speed display interface
    142.
    发明授权

    公开(公告)号:US09953613B2

    公开(公告)日:2018-04-24

    申请号:US14661723

    申请日:2015-03-18

    Applicant: APPLE INC.

    Abstract: Methods and devices employing circuitry for dynamically adjusting bandwidth control of a display interface are provided. The display interface or image content is dynamically adjusted to support both high-speed image data (e.g., 120 Hz image data) and lower-speed content (e.g., 60 Hz content). For example, in some embodiments, additional pixel pipelines and/or processing lanes may be activated during the rendering of high-speed image data, but not during the rendering of low-speed image data. Additionally or alternatively, high-speed image data, but not low-speed data, may be compressed to render high-speed content over an interface that supports only low-speed content.

    Method and apparatus for simplifying communication between a host system and a display subsystem

    公开(公告)号:US09678916B2

    公开(公告)日:2017-06-13

    申请号:US14500944

    申请日:2014-09-29

    Applicant: Apple Inc.

    CPC classification number: G06F13/4221

    Abstract: A method for simplifying the host-to-display subsystem communications and consolidating the non-volatile memory requirements into a PMIC (power management integrated circuit) is disclosed. Hardware and software resource reduction in both the client devices (located in the display subsystem) and the host System on a Chip (SOC) can be realized with a novel PMIC design. The novel PMIC design achieves the resource reduction by providing for the following features: (1) Single-point communication, (2) Single-point notification, (3) Client device status storage, (4) Client device initialization from PMIC non-volatile memory, and (5) Subsystem calibration retrieval from PMIC non-volatile memory.

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