公开(公告)号：US20090296295A1

公开(公告)日：2009-12-03

申请号：US12461237

申请日：2009-08-05

申请人： Ming-Dou Ker ,  Chin-Hao Chen ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Chin-Hao Chen ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.

摘要翻译： 提供了包括夹紧模块和检测模块的ESD保护电路。 夹紧模块耦合在正电源线和负电源线之间。 检测模块包括触发单元，电阻器和MOS电容器。 触发单元的输出端子用于触发夹紧模块。 电阻器耦合在负电源线和触发单元的输入端之间。 MOS电容器耦合在正电源线和用于ESD保护的触发单元的输入端子之间。 在正常的电源操作期间，触发单元的开关端子使MOS电容器耦合在负电源线和触发单元的输入端之间。 由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。

公开(公告)号：US20090267584A1

公开(公告)日：2009-10-29

申请号：US12107902

申请日：2008-04-23

申请人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

发明人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

IPC分类号： G05F5/00

CPC分类号： G01R19/0053 ,  G01R31/002

摘要： A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.

摘要翻译： 耦合在第一电力线和第二电力线之间并包括第一控制单元，设定单元和电压调节单元的瞬态检测电路。 第一控制单元产生第一控制信号。 当静电放电（ESD）事件发生时，第一控制信号处于第一电平。 当ESD事件不发生时，第一控制信号处于第二级。 设置单元设置第一个节点。 当第一控制信号处于第一级时，第一节点被设置在第二级。 电压调节单元调节第一节点。 当第一控制信号处于第二电平时，电压调节单元调节处于第二电平的第一节点的电平。

公开(公告)号：US20090187361A1

公开(公告)日：2009-07-23

申请号：US12018229

申请日：2008-01-23

申请人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

发明人： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

IPC分类号： G01R19/00 ,  G01R29/12

CPC分类号： G01R31/001

摘要： A transient detection circuit including a detecting unit, a setting unit, and a memory unit. The transient detection circuit provides an information signal to an external instrument when an electrostatic discharge (ESD) event occurs. The detecting unit is coupled between a first power line and a second power line for detecting the ESD event. The setting unit sets a level of a first node according to the detection result. The memory unit controls the information signal according to the level of the first node. The information signal is at a first level when the ESD event occurs in the first power line.

摘要翻译： 一种瞬态检测电路，包括检测单元，设定单元和存储单元。 当发生静电放电（ESD）事件时，瞬态检测电路向外部仪器提供信息信号。 检测单元耦合在用于检测ESD事件的第一电力线和第二电力线之间。 设置单元根据检测结果设置第一节点的级别。 存储单元根据第一节点的电平来控制信息信号。 当ESD事件发生在第一电力线中时，信息信号处于第一电平。

公开(公告)号：US20090167663A1

公开(公告)日：2009-07-02

申请号：US12102277

申请日：2008-04-14

申请人： Ming-Dou Ker ,  Hsiao-Wen Zan ,  Ting-Chou Lu

发明人： Ming-Dou Ker ,  Hsiao-Wen Zan ,  Ting-Chou Lu

IPC分类号： G09G3/36 ,  G05F3/02

CPC分类号： G05F3/30 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2320/041

摘要： A liquid crystal display apparatus comprises a system-on-glass (SOG) and a bandgap reference (BGR) circuit. The BGR circuit, which is formed on the SOG, comprises a current mirror set and a diode set. The current mirror set is configured to generate a plurality of fixed currents. The diode set, which is formed by a plurality of diode-connected thin film transistors (TFT), is configured to generate a BGR voltage according to the fixed currents.

摘要翻译： 液晶显示装置包括玻璃系统（SOG）和带隙基准（BGR）电路。 形成在SOG上的BGR电路包括电流镜组和二极管组。 电流镜组被配置为产生多个固定电流。 由多个二极管连接的薄膜晶体管（TFT）形成的二极管组被配置为根据固定电流产生BGR电压。

公开(公告)号：US07554159B2

公开(公告)日：2009-06-30

申请号：US11045300

申请日：2005-01-31

申请人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

发明人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

IPC分类号： H01L23/62

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

摘要翻译： 一种静电放电保护装置，包括第一掺杂剂型的半导体衬底，形成在衬底中的至少一个第二掺杂剂型的源极/漏极对，其中源极/漏极对被分离以在其间限定沟道区域， 限定在源极/漏极对之间并且包括沟道区域的至少一部分的第一掺杂剂类型的掺杂区域，形成在衬底上的栅极电介质层以及形成在栅极介电层上方和沟道区域上方的栅极。

公开(公告)号：US07532047B2

公开(公告)日：2009-05-12

申请号：US11673615

申请日：2007-02-12

申请人： Ming-Dou Ker ,  Fang-Ling Hu

发明人： Ming-Dou Ker ,  Fang-Ling Hu

IPC分类号： H03K3/00

CPC分类号： H03K19/018521

摘要： A mixed-voltage I/O buffer comprises an input circuit, an output circuit, an I/O pad, a pre-driver circuit coupled to the output circuit, two added coupled N-type transistors, and a dynamical gate-controlled circuit coupled to each gate of the two N-type transistors and the pre-driver circuit; one of the N-type transistors is coupled to the input circuit and the output circuit; the other N-type transistor and the dynamic gate-controlled circuit are together coupled to the I/O pad. Thereby, a mixed-voltage I/O buffer which receives 2×VDD-tolerant input signals and overcomes the hot-carrier degradation is realized.

摘要翻译： 混合电压I / O缓冲器包括输入电路，输出电路，I / O焊盘，耦合到输出电路的预驱动器电路，两个相加的耦合的N型晶体管，以及耦合的动态门控电路 到两个N型晶体管和预驱动电路的每个栅极; N型晶体管中的一个耦合到输入电路和输出电路; 另一个N型晶体管和动态栅极控制电路一起耦合到I / O焊盘。 因此，实现了接收2×VDD容许输入信号并克服热载波劣化的混合电压I / O缓冲器。

公开(公告)号：US07525779B2

公开(公告)日：2009-04-28

申请号：US11205378

申请日：2005-08-17

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L29/7436

摘要： Diode strings and electrostatic discharge circuits characterized by low current leakage. Each diode region provides a diode and has first and second regions. The first region is of a first conductive type and formed on a substrate, acting as a first electrode of a diode. The second region is of a second conductive type opposite to the first conductive type, formed in the first region and acting as a second electrode of a corresponding diode. The diodes are forward connected in series to form major anode and cathode of the diode string. An isolation region is of the second conductive type to isolate those diode regions. A bias resistor is connected between the isolation region and a first power line. During normal operation, the voltage of the first power line is not within the range between the voltages of the major anode and cathode.

摘要翻译： 具有低电流泄漏特性的二极管串和静电放电电路。 每个二极管区域提供二极管并且具有第一和第二区域。 第一区域是第一导电类型并且形成在用作二极管的第一电极的衬底上。 第二区域是与第一导电类型相反的第二导电类型，形成在第一区域中并用作相应二极管的第二电极。 二极管串联连接以形成二极管串的主要阳极和阴极。 隔离区域是隔离这些二极管区域的第二导电类型。 偏置电阻连接在隔离区和第一电源线之间。 在正常操作期间，第一电源线的电压不在主阳极和阴极的电压之间的范围内。

公开(公告)号：US07525159B2

公开(公告)日：2009-04-28

申请号：US11768785

申请日：2007-06-26

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L23/62 ,  H01L21/332

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US07504861B2

公开(公告)日：2009-03-17

申请号：US10871348

申请日：2004-06-21

申请人： Che-Hao Chuang ,  Ming-Dou Ker

发明人： Che-Hao Chuang ,  Ming-Dou Ker

IPC分类号： H03K19/0175

CPC分类号： H03K19/00361 ,  H03K19/0013 ,  H03K19/018521

摘要： A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.

摘要翻译： 耦合在以第一电源电压工作的第一电路和以第二电源电压工作的第二电路的混合电压缓冲电路。 缓冲电路可连接到第二电源电压和第三电源电压，并且包括通过第一节点耦合到第一电路的输入电路，并且通过第二节点连接到第二电路。 输入电路包括耦合到第一节点的第一部分和耦合到第二节点的逆变器。 第一部分响应于第一节点上的第一信号，向逆变器提供具有近似等于第三电源电压的电压电平的信号，并且将具有近似等于第二电源电压的电压电平的信号提供给 响应于第一个节点上的第二个信号。

公开(公告)号：US20090032837A1

公开(公告)日：2009-02-05

申请号：US12113410

申请日：2008-05-01

申请人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L29/747

CPC分类号： H01L29/747 ,  H01L27/0262 ,  H01L29/87

摘要： The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.

摘要翻译： 本发明公开了一种不对称双向硅控整流器，其包括：第二导电型衬底; 形成在基板上的第一导电型未掺杂外延层; 第一阱和第二阱都形成在未掺杂的外延层内部并由未掺杂的外延层的一部分分离; 第一掩埋层，形成在所述第一阱和所述衬底之间的接合处; 第二掩埋层，形成在所述第二阱和所述衬底之间的接合处; 在第一阱内形成具有相反导电类型的第一和第二半导体区域; 具有相反导电类型的第三和第四半导体区域都形成在第二阱内部，其中第一和第二半导体区域连接到可控硅整流器的阳极，并且第三和第四半导体区域连接到 硅控整流器。