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    Fin pitch scaling and active layer isolation
    141.
    发明授权
    Fin pitch scaling and active layer isolation 有权
    鳍间距缩放和有源层隔离

    公开(公告)号：US09076842B2

    公开(公告)日：2015-07-07

    申请号：US14011125

    申请日：2013-08-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven John Bentley ,  Bartlomiej Jan Pawlak

    IPC: H01L21/302 ,  H01L21/764 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

    Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

    Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs
    143.
    发明授权
    Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs 有权
    栅极长度独立无硅（SON）方案用于散装FinFET

    公开(公告)号：US09006077B2

    公开(公告)日：2015-04-14

    申请号：US13971937

    申请日：2013-08-21

    Applicant: GlobalFoundries, Inc.

    Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

    IPC: H01L21/76 ,  H01L21/84 ,  H01L21/00 ,  H01L21/762 ,  H01L21/02

    CPC classification number: H01L21/76264 ,  H01L21/02488 ,  H01L21/76224 ,  H01L29/66795

    Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

    Abstract translation: 提供了在具有与绝缘体与衬底隔离的有源沟道区的本体衬底上制造集成电路和FinFET晶体管的方法。 根据示例性实施例，一种用于制造集成电路的方法包括形成覆盖半导体衬底的鳍状结构，其中每个鳍结构包括沟道材料并且在纵向方向上从第一端延伸到第二端。 该方法将锚固材料沉积在翅片结构上。 该方法包括使锚固材料凹入以形成邻近翅片结构的沟槽，其中锚定材料保持与每个翅片结构的第一端和第二端接触。 此外，该方法在半导体衬底和每个鳍结构的沟道材料之间形成空隙，栅极长度独立蚀刻工艺，其中每个鳍结构的沟道材料悬置在半导体衬底上。

    FORMING EMBEDDED SOURCE AND DRAIN REGIONS TO PREVENT BOTTOM LEAKAGE IN A DIELECTRICALLY ISOLATED FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE
    145.
    发明申请
    FORMING EMBEDDED SOURCE AND DRAIN REGIONS TO PREVENT BOTTOM LEAKAGE IN A DIELECTRICALLY ISOLATED FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE 有权
    形成嵌入式源和漏极区域以防止电介质隔离的场效应晶体管（FINFET）器件中的底部漏电

    公开(公告)号：US20150028348A1

    公开(公告)日：2015-01-29

    申请号：US13948374

    申请日：2013-07-23

    Applicant: Globalfoundries Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat K. Akarvardar

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

    Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

    Abstract translation: 提供了用于隔离集成电路（IC）器件（例如，鳍式场效应晶体管（finFET））中的源极和漏极区域的方法。 具体地，FinFET器件包括形成在鳍式衬底上的栅极结构; 栅极结构的有源鳍式沟道下方的隔离氧化物; 形成在栅极结构和隔离氧化物附近的嵌入式源极和漏极（S / D）; 和嵌入式S / D的外延（epi）底部区域，外延底部区域计数器掺杂到嵌入式S / D的极性。 该器件还包括一组注入在epi底部区域下方的注入区域，其中该组注入区域可以是掺杂的，而epi底部区域未被掺杂。 在一种方法中，嵌入式S / D包括用于p沟道金属氧化物半导体场效应晶体管（PMOSFET）的P ++掺杂硅锗（SiGe）和用于n沟道金属氧化物半导体场效应晶体管的N ++氮化硅（SiN） 半导体场效应晶体管（NMOSFET）。

    METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING
    146.
    发明申请
    METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING 审中-公开
    通过现场掺杂分离Si的器件分离方法

    公开(公告)号：US20140374807A1

    公开(公告)日：2014-12-25

    申请号：US13921265

    申请日：2013-06-19

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce B. Doris ,  Ali Khakifirooz

    IPC: H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/785 ,  H01L29/66803

    Abstract: Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation.

    Abstract translation: 本发明的方面涉及一种用于形成在硅衬底上具有一组散热片的集成电路的方法，该散热片组根据预定图案形成。 在沉积外延层之前用N型掺杂剂原位掺杂散热片使冲击穿孔最小化，而外延沉积工艺在掺杂的翅片上施加覆层，沉积导致具有改进的器件隔离的多器件装置。

    Tunable grating couplers
    148.
    发明授权
    Tunable grating couplers 有权

    公开(公告)号：US10816872B1

    公开(公告)日：2020-10-27

    申请号：US16516658

    申请日：2019-07-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

    IPC: G02F1/313 ,  G02F1/295

    Abstract: Structures for a grating coupler and methods of fabricating a structure for a grating coupler. The grating coupler includes a first plurality of grating structures and a second plurality of grating structures that alternate with the first plurality of grating structures in an interleaved arrangement. The first plurality of grating structures are composed of a dielectric material or a semiconductor material. The second plurality of grating structures are composed of a tunable material having a refractive index that changes with an applied voltage.

    Polarizers with confinement cladding
    149.
    发明授权
    Polarizers with confinement cladding 有权

    公开(公告)号：US10816728B1

    公开(公告)日：2020-10-27

    申请号：US16686782

    申请日：2019-11-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

    IPC: G02B6/13 ,  G02B6/43 ,  G02B6/126 ,  G02B6/122 ,  G02B6/12

    Abstract: Structures for a polarizer and methods of fabricating a structure for a polarizer. A first waveguide core has a first width, and a polarizer includes a second waveguide core having a second width that is greater than the first width. The second waveguide core is coupled to the first waveguide core. The polarizer includes a layer that is positioned adjacent to a side surface of the second waveguide core. The layer is comprised of a material having a permittivity with an imaginary part that ranges from 0 to about 15.

    Waveguide intersections incorporating a waveguide crossing
    150.
    发明授权
    Waveguide intersections incorporating a waveguide crossing 有权

    公开(公告)号：US10816725B2

    公开(公告)日：2020-10-27

    申请号：US16134295

    申请日：2018-09-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Abu Thomas

    IPC: G02B6/122 ,  G02B6/125 ,  G02B6/12

    Abstract: Structures with waveguides in multiple levels and methods of fabricating a structure that includes waveguides in multiple levels. A waveguide crossing has a first waveguide and a second waveguide arranged to intersect the first waveguide. A third waveguide is displaced vertically from the waveguide crossing, The third waveguide includes a portion having an overlapping arrangement with a portion of the first waveguide. The overlapping portions of the first and third waveguides are configured to transfer optical signals between the first waveguide and the third waveguide.

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