利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

286 条记录 (耗时 0.032 秒)

    Interconnects with spacer structure for forming air-gaps
    141.
    发明授权
    Interconnects with spacer structure for forming air-gaps 有权

    公开(公告)号：US11164774B2

    公开(公告)日：2021-11-02

    申请号：US16744912

    申请日：2020-01-16

    申请人： International Business Machines Corporation

    发明人： Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Chanro Park ,  Chih-Chao Yang

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    摘要： A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.

    CONFINED GATE RECESSING FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS
    142.
    发明申请
    CONFINED GATE RECESSING FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS 有权

    公开(公告)号：US20210327759A1

    公开(公告)日：2021-10-21

    申请号：US16851652

    申请日：2020-04-17

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Chanro Park ,  Sung Dae Suk ,  Heng Wu

    IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L27/088

    摘要： A method for manufacturing a vertical transistor device includes forming a plurality of fins on a substrate, and forming a gate dielectric layer on the fins and on the substrate adjacent the fins. In the method, one or more sacrificial layers are formed on the gate dielectric layer, and portions of the gate dielectric layer and the one or more sacrificial layers are removed to define a plurality of gate regions. The method also includes depositing a dielectric fill layer in gaps left by the removed gate dielectric and sacrificial layers, and selectively removing the remaining portions of the one or more sacrificial layers to form a plurality of vacant areas in the gate regions. First and second gate structures are respectively formed in first and second vacant areas of the plurality of vacant areas. The first and second gate structures are recessed to a uniform height.

    USING SELECTIVELY FORMED CAP LAYERS TO FORM SELF-ALIGNED CONTACTS TO SOURCE/DRAIN REGIONS
    143.
    发明申请
    USING SELECTIVELY FORMED CAP LAYERS TO FORM SELF-ALIGNED CONTACTS TO SOURCE/DRAIN REGIONS 有权

    公开(公告)号：US20210280690A1

    公开(公告)日：2021-09-09

    申请号：US16810114

    申请日：2020-03-05

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  ChoongHyun Lee ,  Kangguo Cheng ,  Ruilong Xie

    IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02

    摘要： A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the plurality of gate structures. In the method, a germanium oxide layer is formed on the plurality of gate structures and on the plurality of source/drain regions, and portions of the germanium oxide layer on the plurality of source/drain regions are converted into a plurality of dielectric layers. The method also includes removing unconverted portions of the germanium oxide layer from the plurality of gate structures, and depositing a plurality of cap layers in place of the removed unconverted portions of the germanium oxide layer. The plurality of dielectric layers are removed, and a plurality of source/drain contacts are formed on the plurality of source/drain regions. The plurality of source/drain contacts are adjacent the plurality of cap layers.

    REMOVAL OF BARRIER AND LINER LAYERS FROM A BOTTOM OF A VIA
    144.
    发明申请
    REMOVAL OF BARRIER AND LINER LAYERS FROM A BOTTOM OF A VIA 有权

    公开(公告)号：US20210225702A1

    公开(公告)日：2021-07-22

    申请号：US16744984

    申请日：2020-01-16

    申请人： International Business Machines Corporation

    发明人： Chanro Park ,  Koichi Motoyama ,  Kenneth Chun Kuen Cheng ,  Nicholas Anthony Lanzillo

    IPC分类号： H01L21/768

    摘要： A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

    Scalable Device for FINFET Technology
    145.
    发明申请
    Scalable Device for FINFET Technology 有权

    公开(公告)号：US20210217667A1

    公开(公告)日：2021-07-15

    申请号：US16743980

    申请日：2020-01-15

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Kangguo Cheng ,  Juntao Li ,  Chanro Park

    IPC分类号： H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L27/092

    摘要： Scalable device designs for FINFET technology are provided. In one aspect, a method of forming a FINFET device includes: patterning fins in a substrate which include a first fin(s) corresponding to a first FINFET device and a second fin(s) corresponding to a second FINFET device; depositing a conformal gate dielectric over the fins; depositing a conformal sacrificial layer over the gate dielectric; depositing a sacrificial gate material over the sacrificial layer; replacing the sacrificial layer with a first workfunction-setting metal(s) over the first fin(s) and a second workfunction-setting metal(s) over the second fin(s); removing the sacrificial gate material; forming dielectric gates over the first workfunction-setting metal(s), the second workfunction-setting metal(s) and the gate dielectric forming gate stacks; and forming source and drains in the fins between the gate stacks, wherein the source and drains are separated from the gate stacks by inner spacers. A FINFET device is also provided.

    NANOSHEET TRANSISTOR WITH INNER SPACERS
    146.
    发明申请
    NANOSHEET TRANSISTOR WITH INNER SPACERS 有权

    公开(公告)号：US20210210598A1

    公开(公告)日：2021-07-08

    申请号：US16735972

    申请日：2020-01-07

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Ruilong Xie ,  Chanro Park ,  Juntao Li

    IPC分类号： H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    摘要： A method includes forming a stacked nanosheet structure on a semiconductor substrate. The stacked nanosheet structure includes a plurality of alternating sacrificial nanosheets and channel nanosheets. The method further includes forming a dummy gate structure about the stacked nanosheet structure. The method also includes removing outer surface regions of the sacrificial nanosheets to define an at least partial recess at each outer surface region and forming an inner spacer within each of the at least partial recesses. The method also includes forming an isolation layer adjacent at least outer surface regions of at least the channel nanosheets. The method further includes forming a source region and a drain region about the stacked nanosheet structure. The method also includes removing the sacrificial nanosheets through an etching process whereby the isolation layer and the inner spacers isolates the source and drain regions from the etching process.

    Floating gate prevention and capacitance reduction in semiconductor devices
    148.
    发明授权
    Floating gate prevention and capacitance reduction in semiconductor devices 有权

    公开(公告)号：US10978574B2

    公开(公告)日：2021-04-13

    申请号：US16504762

    申请日：2019-07-08

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Kangguo Cheng ,  Chanro Park ,  Juntao Li

    IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

    摘要： A method for fabricating a semiconductor structure includes forming a plurality of vertical fins on a semiconductor substrate. The method further includes depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate. The method further includes forming a plurality of dummy gate structures over each of the vertical fins. The method further includes depositing a hardmask on the dummy gate. The method further includes depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins. The method further includes depositing a second dielectric layer on a portion of the spacer layer. The method further includes recessing spacer layer to expose a portion of the hardmask and the plurality of fins. The method further includes forming a source/drain region on the exposed portion of the plurality of fins.