公开(公告)号：US20250107452A1

公开(公告)日：2025-03-27

申请号：US18472289

申请日：2023-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oscar van der Straten ,  Chih-Chao Yang ,  Koichi Motoyama

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack. A semiconductor device is provided. The semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, where the tunneling barrier comprises a center portion and two outer portions, where the center portion is on an upper horizontal portion of the reference layer, and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer. Forming a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack.

公开(公告)号：US20240304546A1

公开(公告)日：2024-09-12

申请号：US18179417

申请日：2023-03-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oscar van der Straten ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53266

Abstract: A structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a first region and a second region one above another, where the first region comprises a width which increases relative to height, and where the second region comprises a width which decreases relative to height.

公开(公告)号：US12087624B2

公开(公告)日：2024-09-10

申请号：US17481198

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Koichi Motoyama ,  Kenneth Chun Kuen Cheng ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/53238

Abstract: A dielectric layer is located on top of and in contact with a substrate. A conductive line located within the dialectic layer. A barrier layer on top of an in contact with the dielectric layer. The barrier layer is below the conductive line. A liner layer on top of and in contact with the barrier layer and below and in contact with the conductive line. A metal liner on top of and in contact with the conductive line. A capping layer on top of and in contact with the dielectric layer, the barrier layer, the liner layer, and the metal liner.

公开(公告)号：US20240282704A1

公开(公告)日：2024-08-22

申请号：US18171795

申请日：2023-02-21

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Chanro Park ,  Koichi Motoyama ,  John Christopher Arnold

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53257

Abstract: A semiconductor structure is presented including a metal layer having a first pattern, a metal bridge located within the first pattern, at least one via disposed on a portion of the metal layer such that the metal bridge extends to a top surface of the at least one via, and a metal cap disposed directly on top of the at least one via disposed on the portion of the metal layer.

公开(公告)号：US20240153868A1

公开(公告)日：2024-05-09

申请号：US18053772

申请日：2022-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Ruilong Xie ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53266

Abstract: Embodiments of present invention provide an interconnect structure. The interconnect structure includes a first metal line in a first inter-level dielectric (ILD) layer; one or more second metal lines in a second ILD layer above the first metal line and above the first ILD layer; a third metal line in a third ILD layer above the one or more second metal lines and above the second ILD layer; and a skipvia connecting the third metal line with the first metal line, wherein the first, the one or more second, and the third metal lines are made of a first conductive material and the skipvia is made of a second conductive material, and the first conductive material is different from the second conductive material. A method of forming the above interconnect structure is also provided.

公开(公告)号：US20240038535A1

公开(公告)日：2024-02-01

申请号：US17875756

申请日：2022-07-28

Applicant: International Business Machines Corporation

Inventor： Joe Lee ,  Yann Mignot ,  Christopher J. Penny ,  Koichi Motoyama

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0276 ,  H01L21/0335 ,  H01L21/0332

Abstract: A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

公开(公告)号：US20240032435A1

公开(公告)日：2024-01-25

申请号：US17814243

申请日：2022-07-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12 ,  G11C11/161

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes patterning a bottom electrode layer and a first ferromagnetic layer on top of the bottom electrode layer; depositing a dielectric layer, the dielectric layer covering the bottom electrode layer and the first ferromagnetic layer; creating an opening in the dielectric layer, the opening exposing a portion of the first ferromagnetic layer; forming a tunnel barrier layer inside the opening; forming a second ferromagnetic layer on top of the tunnel barrier layer; patterning the tunnel barrier layer and the second ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. Structures formed thereby are also provided.

公开(公告)号：US11854884B2

公开(公告)日：2023-12-26

申请号：US17551531

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Koichi Motoyama ,  Somnath Ghosh ,  Christopher J. Penny ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53295

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

公开(公告)号：US20230402079A1

公开(公告)日：2023-12-14

申请号：US17806790

申请日：2022-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oscar van der Straten ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

CPC classification number: G11C11/161 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/222

Abstract: Embodiments of the invention include a semiconductor structure with a first magneto-resistive random access memory (MRAM) pillar with a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer. The MRAM pillar includes a pillar diameter. The semiconductor structure also includes a coaxial top electrode with a top diameter that is less than the pillar diameter.

公开(公告)号：US11798842B2

公开(公告)日：2023-10-24

申请号：US17482939

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chanro Park ,  Koichi Motoyama ,  Hsueh-Chung Chen ,  Yann Mignot

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76843 ,  H01L21/30608 ,  H01L21/7688 ,  H01L21/76879 ,  H01L21/76897

Abstract: Semiconductor devices and methods of forming conductive lines in the same include forming a cut region in a first dielectric layer, the cut region having a first width. A second dielectric plug is formed in the cut region. A mask is formed, over the first dielectric layer, that defines at least one trench region that crosses the second dielectric plug, with the at least one trench region having a second width that is smaller than the first width. Material from the first dielectric layer in the trench regions is etched away, using a selective anisotropic etch that leaves the second dielectric plug in place, to form trenches in the first dielectric layer. Conductive material is deposited in the trenches to form conductive lines that are separated by the second dielectric plug.