公开(公告)号：US09274973B2

公开(公告)日：2016-03-01

申请号：US14269445

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F12/1045 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1004 ,  G06F2212/7201 ,  Y02D10/13

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

公开(公告)号：US20160027497A1

公开(公告)日：2016-01-28

申请号：US14878452

申请日：2015-10-08

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/4094

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括耦合到阵列的存储器单元阵列和感测电路。 感测电路被配置为使用存储在耦合到感测线的第一存储器单元中的数据值作为第一输入和存储在耦合到感测线的第二存储器单元中的数据值作为第二输入来执行逻辑运算。 感测电路被配置为执行逻辑操作而不经由感测线地址访问传送数据。

公开(公告)号：US09158667B2

公开(公告)日：2015-10-13

申请号：US13784219

申请日：2013-03-04

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/10 ,  G06F12/00 ,  G11C15/00 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括耦合到阵列的存储器单元阵列和感测电路。 感测电路被配置为使用存储在耦合到感测线的第一存储器单元中的数据值作为第一输入和存储在耦合到感测线的第二存储器单元中的数据值作为第二输入来执行逻辑运算。 感测电路被配置为执行逻辑操作而不经由感测线地址访问传送数据。

公开(公告)号：US20150279466A1

公开(公告)日：2015-10-01

申请号：US14667868

申请日：2015-03-25

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C15/04

CPC classification number: G11C15/043 ,  G11C7/1006 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.

Abstract translation: 本公开包括与比较存储器中的数据模式相关的装置和方法。 示例性方法可以包括将存储在存储器阵列中的多个数据模式与目标数据模式进行比较。 该方法可以包括确定数据模式数量的数据模式是否与目标数据模式匹配，而不经由输入/输出（I / O）线路从存储器阵列传送数据。

公开(公告)号：US09128637B2

公开(公告)日：2015-09-08

申请号：US14194095

申请日：2014-02-28

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G06F3/06 ,  G06F11/16 ,  G11C29/00 ,  G06F11/20

CPC classification number: G06F3/0679 ,  G06F3/0604 ,  G06F3/0659 ,  G06F11/1666 ,  G06F11/20 ,  G06F2003/0697 ,  G11C16/34 ,  G11C29/52 ,  G11C29/74 ,  G11C29/82

Abstract: The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.

Abstract translation: 本公开包括用于逻辑单元操作的方法和装置。 一个设备实施例包括多个逻辑单元，其中多个逻辑单元中的每一个具有唯一的地址。 该设备包括耦合到多个逻辑单元的控制电路，并且被配置为可选择地使用多个命令和一个地址之一控制多个逻辑单元的多于一个。

公开(公告)号：US09052842B2

公开(公告)日：2015-06-09

申请号：US14194095

申请日：2014-02-28

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G06F3/06 ,  G06F11/16 ,  G11C29/00 ,  G06F11/20

Abstract: The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.

公开(公告)号：US08971124B1

公开(公告)日：2015-03-03

申请号：US13962399

申请日：2013-08-08

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C16/04 ,  H03K19/00

CPC classification number: G11C7/22 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/068 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/0013 ,  H03K19/1776

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括存储器单元阵列和感测电路，该电路包括耦合到该阵列的感测线的主锁存器。 感测电路可以被配置为通过感测耦合到感测线的存储器单元来执行逻辑操作的第一操作阶段，通过感测耦合到所述逻辑操作的相应数量的不同存储器单元执行逻辑操作的多个中间操作阶段 并且在不执行感测线地址访问的情况下，累积第一操作阶段的结果和耦合到主锁存器的次锁存器中的中间操作相位的数量。

公开(公告)号：US08964496B2

公开(公告)日：2015-02-24

申请号：US13952054

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C29/00 ,  G11C7/02 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract translation: 本公开包括与使用感测电路执行比较和/或报告操作相关的装置和方法。 示例性方法可以包括将存储器阵列的输入/输出（IO）线充电到电压。 该方法可以包括确定存储在存储器阵列中的数据是否与比较值相匹配。 确定存储的数据是否与比较值匹配可以包括激活存储器阵列的多个访问线。 该确定可以包括感测耦合到接入线路数量的多个存储器单元。 该确定可以包括检测IO线的电压是否响应于对应于存储器单元的数量的所选择的解码线的激活而改变。

公开(公告)号：US20140297990A1

公开(公告)日：2014-10-02

申请号：US14269445

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

IPC: G06F12/10

CPC classification number: G06F12/1045 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1004 ,  G06F2212/7201 ,  Y02D10/13

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。

公开(公告)号：US20140250279A1

公开(公告)日：2014-09-04

申请号：US13784219

申请日：2013-03-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Troy A. Manning

IPC: G06F12/00

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括耦合到阵列的存储器单元阵列和感测电路。 感测电路被配置为使用存储在耦合到感测线的第一存储器单元中的数据值作为第一输入和存储在耦合到感测线的第二存储器单元中的数据值作为第二输入来执行逻辑运算。 感测电路被配置为执行逻辑操作而不经由感测线地址访问传送数据。