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    Three-dimensional memory device including an inter-tier etch stop layer and method of making the same
    144.
    发明授权
    Three-dimensional memory device including an inter-tier etch stop layer and method of making the same 有权

    公开(公告)号：US11296101B2

    公开(公告)日：2022-04-05

    申请号：US16833378

    申请日：2020-03-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yao-Sheng Lee ,  Senaka Kanakamedala ,  Raghuveer S. Makala ,  Johann Alsmeier

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02

    Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.

    Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same
    147.
    发明授权
    Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same 有权

    公开(公告)号：US11201139B2

    公开(公告)日：2021-12-14

    申请号：US16825304

    申请日：2020-03-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Senaka Kanakamedala ,  Fei Zhou

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

    Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same
    150.
    发明授权
    Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same 有权

    公开(公告)号：US11114534B2

    公开(公告)日：2021-09-07

    申请号：US16728825

    申请日：2019-12-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Adarsh Rajashekhar ,  Fei Zhou ,  Raghuveer S. Makala ,  Yanli Zhang ,  Rahul Sharangpani

    IPC: H01L29/417 ,  H01L27/11597 ,  H01L27/11582 ,  H01L27/11556

    Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

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