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公开(公告)号:US20200321249A1
公开(公告)日:2020-10-08
申请号:US16908348
申请日:2020-06-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hsin Chang , Fang Wen Tsai , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng
IPC: H01L21/768 , H01L23/48 , H01L23/544 , H01L23/00 , H01L21/683
Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
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公开(公告)号:US20200312791A1
公开(公告)日:2020-10-01
申请号:US16901516
申请日:2020-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Po-Hao Tsai , Jui-Pin Hung , Jing-Cheng Lin
IPC: H01L23/00 , H01L23/498 , H01L25/10 , H01L21/48 , H01L23/538 , H01L21/78 , H01L21/56 , H01L25/00 , H01L23/31
Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
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公开(公告)号:US20200303275A1
公开(公告)日:2020-09-24
申请号:US16895415
申请日:2020-06-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Lin Huang , Jung-Hua Chang , Jy-Jie Gau , Jing-Cheng Lin
IPC: H01L23/31 , H01L23/498 , H01L21/48 , H01L23/538 , H01L23/00 , H01L25/10 , H01L25/00
Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
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公开(公告)号:US20200294983A1
公开(公告)日:2020-09-17
申请号:US16886795
申请日:2020-05-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Li-Hui Cheng , Jing-Cheng Lin , Po-Hao Tsai
IPC: H01L25/00 , H01L21/56 , H01L25/10 , H01L23/00 , H01L21/50 , H01L21/683 , H01L23/498 , H01L23/538
Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
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公开(公告)号:US10672723B2
公开(公告)日:2020-06-02
申请号:US16392815
申请日:2019-04-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jing-Cheng Lin , Chin-Chuan Chang , Jui-Pin Hung
IPC: H01L23/00 , H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56 , H01L25/03 , H01L25/00 , H01L25/065 , H01L25/10
Abstract: Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.
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公开(公告)号:US10522476B2
公开(公告)日:2019-12-31
申请号:US15652247
申请日:2017-07-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Li-Hui Cheng , Jing-Cheng Lin , Po-Hao Tsai
IPC: H01L23/00 , H01L23/538 , H01L23/31 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/498 , H01L25/10 , H01L21/683 , H01L23/50
Abstract: A package structure including an integrated fan-out package and plurality of conductive terminals is provided. The integrated fan-out package includes an integrated circuit component, a plurality of conductive through vias, an insulating encapsulation having a first surface and a second surface opposite to the first surface, and a redistribution circuit structure. The insulating encapsulation laterally encapsulates the conductive through vias and the integrated circuit component. Each of conductive through vias includes a protruding portion accessibly revealed by the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit component and covers the first surface of the insulating encapsulation and the integrated circuit component. The conductive terminals are disposed on and electrically connected to the protruding portions of the conductive through vias, and a plurality of intermetallic compound caps are formed between the conductive terminals and the protruding portions.
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公开(公告)号:US10510684B2
公开(公告)日:2019-12-17
申请号:US15911765
申请日:2018-03-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Wei Wu , Ying-Ching Shih , Szu-Wei Lu , Jing-Cheng Lin
IPC: H01L23/00 , H01L25/065 , H01L25/00 , H01L23/14 , H01L23/48 , H01L23/498 , H01L23/31
Abstract: Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.
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公开(公告)号:US10340253B2
公开(公告)日:2019-07-02
申请号:US15716506
申请日:2017-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shu-Hang Liao , Chih-Wei Wu , Jing-Cheng Lin , Szu-Wei Lu , Ying-Ching Shih
IPC: H01L25/065 , H01L21/56 , H01L23/31 , H01L23/00
Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsualnt. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.
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公开(公告)号:US10157870B1
公开(公告)日:2018-12-18
申请号:US15716494
申请日:2017-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Wei Wu , Jing-Cheng Lin , Szu-Wei Lu , Ying-Ching Shih
IPC: H01L23/12 , H01L23/00 , H01L21/768 , H01L23/522 , H01L23/31 , H01L21/683 , H01L23/532
Abstract: A method of fabricating an integrated fan-out package is described. The method includes the following steps. A carrier is provided. Through insulator vias are formed on the carrier, and at least one semiconductor die is provided on the carrier. The semiconductor die is attached to the carrier through a die attach film. An insulating encapsulant having a first region and a second region is formed on the carrier. The insulating encapsulant in the first region is encapsulating the semiconductor die, and the insulating encapsulant in the second region is encapsulating the plurality of through insulator vias. The carrier is debonded, and a trimming process is performed to remove portions of the insulating encapsulant in the second region, and a trench is formed in the insulating encapsulant in the second region. A plurality of conductive balls is disposed on the insulating encapsulant in the second region. The plurality of conductive balls surround the first region of the insulating encapsulant and the die attach film, and is electrically connected to the plurality of through insulator vias.
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公开(公告)号:US10134719B2
公开(公告)日:2018-11-20
申请号:US15235118
申请日:2016-08-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Li-Hui Cheng , Jing-Cheng Lin , Po-Hao Tsai
IPC: H01L25/00 , H01L21/48 , H01L21/50 , H01L21/56 , H01L21/683 , H01L23/498 , H01L23/538 , H01L23/00 , H01L21/60
Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
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