公开(公告)号：US20200295001A1

公开(公告)日：2020-09-17

申请号：US16887138

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench within the substrate. The trench surrounds the source region and the drain region. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate metal having a first sidewall and a second gate metal having a first outer sidewall that contacts the first sidewall directly over the upper surface of the substrate.

公开(公告)号：US20200258892A1

公开(公告)日：2020-08-13

申请号：US16860234

申请日：2020-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L27/11 ,  G06F30/398 ,  G06F30/39 ,  G11C29/12 ,  G11C29/04 ,  G11C29/08 ,  G11C29/50 ,  H01L23/528

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US10741555B2

公开(公告)日：2020-08-11

申请号：US16574205

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a source region and a drain region. The drain region is separated from the source region by a channel region. An isolation structure surrounds the source region, the drain region, and the channel region. A gate structure is over the channel region. The gate structure includes a first gate electrode region having one or more first materials and a second gate electrode region having one or more second materials that are different than the one or more first materials. The second gate electrode region continuously extends between a first outermost sidewall directly over the isolation structure and a second outermost sidewall directly over the channel region.

公开(公告)号：US20200058749A1

公开(公告)日：2020-02-20

申请号：US16661108

申请日：2019-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/06

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having interior surfaces that define a trench within an upper surface of the substrate. One or more dielectric materials are disposed within the trench. A source region disposed within the substrate and a drain region is disposed within of the substrate and separated from the source region along a first direction. A gate structure is over the upper surface of the substrate between the source region and the drain region. The upper surface of the substrate has a first width directly below the gate structure that is larger than a second width of the upper surface of the substrate within the source region or the drain region. The first width and the second width are measured along a second direction that is perpendicular to the first direction.

公开(公告)号：US20200027845A1

公开(公告)日：2020-01-23

申请号：US16587819

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

公开(公告)号：US20190393234A1

公开(公告)日：2019-12-26

申请号：US16051721

申请日：2018-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L29/788

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

公开(公告)号：US20190378905A1

公开(公告)日：2019-12-12

申请号：US16550497

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming an isolation structure within an upper surface of a substrate. The isolation structure surrounds a continuous region of the substrate defining a source area, a drain area, and a channel area. A gate structure is formed over the channel area. An implantation process is performed to form a source region within the source area and a drain region within the drain area. The channel area is arranged between the source region and the drain region along a first direction and extends past the source region and the drain region along a second direction that is perpendicular to the first direction. The first direction and the second direction are parallel to the upper surface of the substrate.

公开(公告)号：US20190067300A1

公开(公告)日：2019-02-28

申请号：US15903770

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L27/11 ,  H01L23/528 ,  G11C29/08 ,  G06F17/50 ,  G11C29/50

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US09502585B2

公开(公告)日：2016-11-22

申请号：US14690209

申请日：2015-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chien-Chih Chou ,  Chih-Wen Hsiung ,  Kong-Beng Thei

IPC: H01L29/872 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L29/06 ,  H01L29/47 ,  H01L21/225

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/66143

Abstract: A method of manufacturing a Schottky barrier diode is provided, which includes: providing a semiconductor substrate including a first well region of a first conductivity type in the semiconductor substrate; forming a surface-doped layer having a dopant of a second conductivity type opposite to the first conductivity type in the first well region; forming a dielectric layer in contact with the surface-doped layer; performing a thermal treatment on the surface-doped layer to move the dopant of the surface-doped layer in the dielectric layer; removing the dielectric layer to expose the first well region; and forming a silicide layer in contact with the exposed first well region. A Schottky barrier diode is also provided.

Abstract translation: 提供一种制造肖特基势垒二极管的方法，其包括：在半导体衬底中提供包括第一导电类型的第一阱区的半导体衬底; 在所述第一阱区中形成具有与所述第一导电类型相反的第二导电类型的掺杂剂的表面掺杂层; 形成与表面掺杂层接触的介电层; 对所述表面掺杂层进行热处理，以移动所述介电层中的所述表面掺杂层的掺杂剂; 去除介电层以露出第一阱区; 以及形成与暴露的第一阱区域接触的硅化物层。 还提供肖特基势垒二极管。

公开(公告)号：US12148752B2

公开(公告)日：2024-11-19

申请号：US17815180

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.